Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.76	98.25	93.31	90.85	87.79	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.19	99.92	92.06	47.04	87.79	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T11,T19

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T20,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T10,T21	Yes	T5,T10,T21	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T25,T11,T26	Yes	T25,T11,T26	INPUT
edn_i[2].edn_req	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
edn_i[3].edn_req	Yes	Yes	T9,T10,T20	Yes	T9,T10,T20	INPUT
edn_i[4].edn_req	Yes	Yes	T10,T17,T8	Yes	T10,T17,T8	INPUT
edn_i[5].edn_req	Yes	Yes	T28,T30,T13	Yes	T28,T30,T13	INPUT
edn_i[6].edn_req	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T11,T26,T34	Yes	T11,T26,T34	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T26,T30,T35	Yes	T26,T30,T13	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T25,T11,T26	Yes	T25,T11,T26	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T27,T29,T30	Yes	T27,T28,T29	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T27,T30,T36	Yes	T27,T30,T36	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T28,T37	Yes	T9,T10,T28	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T10,T20,T28	Yes	T9,T10,T20	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T9,T10,T20	Yes	T9,T10,T20	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T10,T17,T36	Yes	T10,T17,T38	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T17,T39,T33	Yes	T10,T17,T38	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T10,T17,T38	Yes	T10,T17,T38	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T28,T30,T13	Yes	T28,T30,T13	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T28,T30,T33	Yes	T28,T30,T13	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T28,T30,T13	Yes	T28,T30,T13	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T32,T33,T40	Yes	T32,T33,T40	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T31,T33,T41	Yes	T31,T33,T40	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T10,T11,T42	Yes	T10,T11,T42	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T11,T43	Yes	T10,T11,T43	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T20,T43	Yes	T5,T20,T43	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T11,T43	Yes	T10,T11,T43	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T20,T43	Yes	T5,T20,T43	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T4,T44	Yes	T1,T4,T44	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	221011153	220908816	0	0
CsrngAppIfOut_A	221011153	220908816	0	0
FpvSecCmCntAlertCheck_A	221011153	33	0	0
FpvSecCmGenCmdFifoRptrCheck_A	221011153	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	221011153	0	0	0
FpvSecCmMainFsmCheck_A	221011153	0	0	0
FpvSecCmRegWeOnehotCheck_A	221011153	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	221011153	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	221011153	0	0	0
IntrEdnCmdReqDoneKnownO_A	221011153	220908816	0	0
TlAReadyKnownO_A	221011153	220908816	0	0
TlDValidKnownO_A	221011153	220908816	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	221011153	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	221011153	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	221011153	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	221011153	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	221011153	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	221011153	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	221011153	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	221011153	484428	0	316
gen_edn_if_asserts[0].EdnDataStable_A	221011153	20225	0	412
gen_edn_if_asserts[0].EdnEndPointOut_A	221011153	220908816	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	221011153	89850	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	221011153	484428	0	316
gen_edn_if_asserts[1].EdnDataStable_A	221011153	4962	0	119
gen_edn_if_asserts[1].EdnEndPointOut_A	221011153	220908816	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	221011153	89850	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	221011153	484428	0	316
gen_edn_if_asserts[2].EdnDataStable_A	221011153	4039	0	125
gen_edn_if_asserts[2].EdnEndPointOut_A	221011153	220908816	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	221011153	89850	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	221011153	484428	0	316
gen_edn_if_asserts[3].EdnDataStable_A	221011153	4880	0	124
gen_edn_if_asserts[3].EdnEndPointOut_A	221011153	220908816	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	221011153	89850	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	221011153	484428	0	316
gen_edn_if_asserts[4].EdnDataStable_A	221011153	7295	0	96
gen_edn_if_asserts[4].EdnEndPointOut_A	221011153	220908816	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	221011153	89850	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	221011153	484428	0	316
gen_edn_if_asserts[5].EdnDataStable_A	221011153	2831	0	90
gen_edn_if_asserts[5].EdnEndPointOut_A	221011153	220908816	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	221011153	89850	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	221011153	484428	0	316
gen_edn_if_asserts[6].EdnDataStable_A	221011153	2025	0	82
gen_edn_if_asserts[6].EdnEndPointOut_A	221011153	220908816	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	221011153	89850	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	33	0	0
T8	1095	1	0	0
T12	1779	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	3338	0	0	0
T30	2326	0	0	0
T31	974	0	0	0
T34	1097	0	0	0
T42	575	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	1955	0	0	0
T53	1489	0	0	0
T54	1585	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	484428	0	316
T1	17348	1354	0	0
T2	2221	34	0	0
T3	1087	13	0	0
T4	11910	6892	0	2
T5	2006	1017	0	0
T9	3784	279	0	0
T10	1614	275	0	0
T18	0	0	0	2
T20	727	206	0	0
T21	1039	25	0	0
T22	0	0	0	2
T23	0	0	0	2
T27	5763	35	0	0
T38	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	20225	0	412
T1	17348	17	0	0
T2	2221	63	0	1
T3	1087	3	0	1
T4	11910	9	0	0
T5	2006	1	0	0
T9	3784	495	0	1
T10	1614	0	0	0
T17	0	68	0	1
T19	0	0	0	1
T20	727	0	0	0
T21	1039	3	0	1
T27	5763	0	0	0
T28	0	0	0	1
T37	0	0	0	1
T44	0	3	0	0
T57	0	3	0	1
T58	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	89850	0	0
T5	2006	22	0	0
T6	0	283	0	0
T7	0	344	0	0
T8	0	524	0	0
T10	1614	0	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T20	727	28	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T31	0	389	0	0
T42	0	255	0	0
T43	1329	0	0	0
T59	0	368	0	0
T60	0	34	0	0
T61	0	182	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	484428	0	316
T1	17348	1354	0	0
T2	2221	34	0	0
T3	1087	13	0	0
T4	11910	6892	0	2
T5	2006	1017	0	0
T9	3784	279	0	0
T10	1614	275	0	0
T18	0	0	0	2
T20	727	206	0	0
T21	1039	25	0	0
T22	0	0	0	2
T23	0	0	0	2
T27	5763	35	0	0
T38	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	4962	0	119
T11	2833	4	0	1
T13	0	3	0	1
T17	3460	0	0	0
T19	3241	0	0	0
T25	890	4	0	0
T26	3494	43	0	1
T28	3389	3	0	1
T30	0	63	0	1
T33	0	3	0	1
T34	0	4	0	0
T35	0	51	0	1
T39	0	11	0	1
T43	1329	0	0	0
T44	4257	0	0	0
T55	1457	0	0	0
T57	1679	0	0	0
T62	0	0	0	1
T63	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	89850	0	0
T5	2006	22	0	0
T6	0	283	0	0
T7	0	344	0	0
T8	0	524	0	0
T10	1614	0	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T20	727	28	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T31	0	389	0	0
T42	0	255	0	0
T43	1329	0	0	0
T59	0	368	0	0
T60	0	34	0	0
T61	0	182	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	484428	0	316
T1	17348	1354	0	0
T2	2221	34	0	0
T3	1087	13	0	0
T4	11910	6892	0	2
T5	2006	1017	0	0
T9	3784	279	0	0
T10	1614	275	0	0
T18	0	0	0	2
T20	727	206	0	0
T21	1039	25	0	0
T22	0	0	0	2
T23	0	0	0	2
T27	5763	35	0	0
T38	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	4039	0	125
T11	2833	0	0	0
T13	0	3	0	1
T15	0	1	0	0
T17	3460	0	0	0
T20	727	0	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	61	0	1
T28	0	3	0	1
T29	0	4	0	1
T30	0	52	0	1
T33	0	62	0	1
T36	0	4	0	0
T41	0	3	0	1
T43	1329	0	0	0
T44	4257	0	0	0
T57	1679	0	0	0
T64	0	3	0	1
T65	0	0	0	1
T66	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	89850	0	0
T5	2006	22	0	0
T6	0	283	0	0
T7	0	344	0	0
T8	0	524	0	0
T10	1614	0	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T20	727	28	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T31	0	389	0	0
T42	0	255	0	0
T43	1329	0	0	0
T59	0	368	0	0
T60	0	34	0	0
T61	0	182	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	484428	0	316
T1	17348	1354	0	0
T2	2221	34	0	0
T3	1087	13	0	0
T4	11910	6892	0	2
T5	2006	1017	0	0
T9	3784	279	0	0
T10	1614	275	0	0
T18	0	0	0	2
T20	727	206	0	0
T21	1039	25	0	0
T22	0	0	0	2
T23	0	0	0	2
T27	5763	35	0	0
T38	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	4880	0	124
T4	11910	0	0	0
T5	2006	0	0	0
T9	3784	3	0	1
T10	1614	4	0	0
T11	2833	0	0	0
T20	727	1	0	0
T21	1039	0	0	0
T25	890	0	0	0
T27	5763	0	0	0
T28	0	47	0	1
T30	0	3	0	1
T33	0	3	0	1
T37	0	61	0	1
T41	0	0	0	1
T43	1329	0	0	0
T65	0	0	0	1
T67	0	54	0	1
T68	0	3	0	1
T69	0	8	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	89850	0	0
T5	2006	22	0	0
T6	0	283	0	0
T7	0	344	0	0
T8	0	524	0	0
T10	1614	0	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T20	727	28	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T31	0	389	0	0
T42	0	255	0	0
T43	1329	0	0	0
T59	0	368	0	0
T60	0	34	0	0
T61	0	182	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	484428	0	316
T1	17348	1354	0	0
T2	2221	34	0	0
T3	1087	13	0	0
T4	11910	6892	0	2
T5	2006	1017	0	0
T9	3784	279	0	0
T10	1614	275	0	0
T18	0	0	0	2
T20	727	206	0	0
T21	1039	25	0	0
T22	0	0	0	2
T23	0	0	0	2
T27	5763	35	0	0
T38	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	7295	0	96
T10	1614	4	0	1
T11	2833	0	0	0
T13	0	3	0	1
T17	3460	58	0	1
T20	727	0	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T33	0	67	0	1
T36	0	4	0	1
T38	0	4	0	0
T39	0	56	0	1
T41	0	42	0	1
T43	1329	0	0	0
T57	1679	0	0	0
T65	0	0	0	1
T70	0	4	0	1
T71	0	17	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	89850	0	0
T5	2006	22	0	0
T6	0	283	0	0
T7	0	344	0	0
T8	0	524	0	0
T10	1614	0	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T20	727	28	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T31	0	389	0	0
T42	0	255	0	0
T43	1329	0	0	0
T59	0	368	0	0
T60	0	34	0	0
T61	0	182	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	484428	0	316
T1	17348	1354	0	0
T2	2221	34	0	0
T3	1087	13	0	0
T4	11910	6892	0	2
T5	2006	1017	0	0
T9	3784	279	0	0
T10	1614	275	0	0
T18	0	0	0	2
T20	727	206	0	0
T21	1039	25	0	0
T22	0	0	0	2
T23	0	0	0	2
T27	5763	35	0	0
T38	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	2831	0	90
T6	1255	0	0	0
T7	1104	0	0	0
T8	1095	0	0	0
T13	0	3	0	1
T28	3389	19	0	1
T29	2303	0	0	0
T30	0	54	0	1
T33	0	54	0	1
T34	1097	0	0	0
T37	3693	0	0	0
T41	0	3	0	1
T58	1346	0	0	0
T65	0	3	0	1
T71	0	30	0	1
T72	0	4	0	1
T73	0	16	0	1
T74	0	61	0	1
T75	9921	0	0	0
T76	1942	0	0	0

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	89850	0	0
T5	2006	22	0	0
T6	0	283	0	0
T7	0	344	0	0
T8	0	524	0	0
T10	1614	0	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T20	727	28	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T31	0	389	0	0
T42	0	255	0	0
T43	1329	0	0	0
T59	0	368	0	0
T60	0	34	0	0
T61	0	182	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	484428	0	316
T1	17348	1354	0	0
T2	2221	34	0	0
T3	1087	13	0	0
T4	11910	6892	0	2
T5	2006	1017	0	0
T9	3784	279	0	0
T10	1614	275	0	0
T18	0	0	0	2
T20	727	206	0	0
T21	1039	25	0	0
T22	0	0	0	2
T23	0	0	0	2
T27	5763	35	0	0
T38	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T53	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	2025	0	82
T12	1779	0	0	0
T18	3338	0	0	0
T22	134651	0	0	0
T30	2326	0	0	0
T31	974	1	0	0
T32	0	4	0	0
T33	0	33	0	1
T40	0	4	0	0
T41	0	31	0	1
T42	575	0	0	0
T52	1955	0	0	0
T53	1489	0	0	0
T54	1585	0	0	0
T59	833	0	0	0
T77	0	3	0	1
T78	0	4	0	1
T79	0	20	0	1
T80	0	3	0	1
T81	0	3	0	1
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	89850	0	0
T5	2006	22	0	0
T6	0	283	0	0
T7	0	344	0	0
T8	0	524	0	0
T10	1614	0	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T20	727	28	0	0
T21	1039	0	0	0
T25	890	0	0	0
T26	3494	0	0	0
T27	5763	0	0	0
T31	0	389	0	0
T42	0	255	0	0
T43	1329	0	0	0
T59	0	368	0	0
T60	0	34	0	0
T61	0	182	0	0