Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	221503686	9931781	0	0
boot_gen_cmd_rd_A	221503686	52115	0	0
boot_ins_cmd_rd_A	221503686	60529	0	0
ctrl_rd_A	221503686	52625	0	0
err_code_test_rd_A	221503686	59566	0	0
intr_enable_rd_A	221503686	57907	0	0
max_num_reqs_between_reseeds_rd_A	221503686	53212	0	0
regwen_rd_A	221503686	62102	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	9931781	0	0
T13	4018	0	0	0
T22	134651	58369	0	0
T23	459006	261461	0	0
T24	0	142494	0	0
T36	1483	0	0	0
T38	2987	0	0	0
T39	3736	0	0	0
T56	1082	0	0	0
T59	833	0	0	0
T133	0	180426	0	0
T134	0	286767	0	0
T142	1850	0	0	0
T225	0	121950	0	0
T226	0	263539	0	0
T227	0	161510	0	0
T228	0	344307	0	0
T229	0	231445	0	0
T230	1885	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	52115	0	0
T14	2917	0	0	0
T24	420199	4212	0	0
T70	2267	0	0	0
T132	3417	0	0	0
T134	0	4279	0	0
T136	2355	0	0	0
T139	2710	0	0	0
T146	1952	0	0	0
T226	0	7318	0	0
T231	0	3345	0	0
T232	0	3097	0	0
T233	0	3047	0	0
T234	0	7709	0	0
T235	0	2246	0	0
T236	0	2990	0	0
T237	0	2116	0	0
T238	996	0	0	0
T239	1897	0	0	0
T240	1455	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	60529	0	0
T14	2917	0	0	0
T24	420199	4783	0	0
T70	2267	0	0	0
T132	3417	0	0	0
T134	0	4885	0	0
T136	2355	0	0	0
T139	2710	0	0	0
T146	1952	0	0	0
T226	0	8879	0	0
T231	0	3828	0	0
T232	0	3227	0	0
T233	0	3783	0	0
T234	0	8836	0	0
T235	0	2762	0	0
T236	0	3865	0	0
T237	0	2276	0	0
T238	996	0	0	0
T239	1897	0	0	0
T240	1455	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	52625	0	0
T11	2833	0	0	0
T17	3460	0	0	0
T19	3241	0	0	0
T20	727	2	0	0
T24	0	4374	0	0
T25	890	0	0	0
T26	3494	0	0	0
T43	1329	0	0	0
T44	4257	0	0	0
T55	1457	0	0	0
T57	1679	0	0	0
T98	0	1	0	0
T134	0	4406	0	0
T226	0	7497	0	0
T231	0	3289	0	0
T241	0	7	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	59566	0	0
T14	2917	0	0	0
T24	420199	4706	0	0
T70	2267	0	0	0
T132	3417	0	0	0
T134	0	5041	0	0
T136	2355	0	0	0
T139	2710	0	0	0
T146	1952	0	0	0
T226	0	8583	0	0
T231	0	3617	0	0
T232	0	3443	0	0
T233	0	3422	0	0
T234	0	9109	0	0
T235	0	2716	0	0
T236	0	3633	0	0
T237	0	2199	0	0
T238	996	0	0	0
T239	1897	0	0	0
T240	1455	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	57907	0	0
T8	1095	0	0	0
T18	3338	0	0	0
T24	0	4744	0	0
T30	2326	0	0	0
T31	974	0	0	0
T34	1097	0	0	0
T42	575	0	0	0
T52	1955	0	0	0
T53	1489	0	0	0
T75	9921	35	0	0
T76	1942	0	0	0
T134	0	4685	0	0
T226	0	7737	0	0
T231	0	3619	0	0
T241	0	93	0	0
T245	0	7	0	0
T246	0	27	0	0
T247	0	33	0	0
T248	0	42	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	53212	0	0
T14	2917	0	0	0
T24	420199	4321	0	0
T70	2267	0	0	0
T132	3417	0	0	0
T134	0	4445	0	0
T136	2355	0	0	0
T139	2710	0	0	0
T146	1952	0	0	0
T226	0	7642	0	0
T231	0	3171	0	0
T232	0	2891	0	0
T233	0	2850	0	0
T234	0	7813	0	0
T235	0	2301	0	0
T236	0	3299	0	0
T237	0	2091	0	0
T238	996	0	0	0
T239	1897	0	0	0
T240	1455	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221503686	62102	0	0
T14	2917	0	0	0
T24	420199	5136	0	0
T70	2267	0	0	0
T132	3417	0	0	0
T134	0	4731	0	0
T136	2355	0	0	0
T139	2710	0	0	0
T146	1952	0	0	0
T226	0	8895	0	0
T231	0	3969	0	0
T232	0	3637	0	0
T233	0	3546	0	0
T234	0	9204	0	0
T235	0	2512	0	0
T236	0	3797	0	0
T237	0	2442	0	0
T238	996	0	0	0
T239	1897	0	0	0
T240	1455	0	0	0