Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.56	98.25	93.31	90.85	86.63	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	86.99	99.92	92.06	47.04	86.63	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T16,T17

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T16,T15	Yes	T4,T16,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T3,T4,T18	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T12,T22,T23	Yes	T12,T22,T23	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T8,T24	Yes	T1,T8,T24	INPUT
edn_i[3].edn_req	Yes	Yes	T16,T12,T24	Yes	T16,T12,T24	INPUT
edn_i[4].edn_req	Yes	Yes	T8,T23,T25	Yes	T8,T23,T25	INPUT
edn_i[5].edn_req	Yes	Yes	T26,T27,T23	Yes	T26,T27,T23	INPUT
edn_i[6].edn_req	Yes	Yes	T23,T28,T25	Yes	T23,T28,T25	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T18,T7,T19	Yes	T18,T7,T19	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T22,T23,T28	Yes	T22,T23,T28	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T29,T30,T31	Yes	T12,T23,T28	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T12,T22,T23	Yes	T12,T22,T23	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T8,T24,T15	Yes	T8,T24,T15	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T24,T15,T23	Yes	T24,T15,T27	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T8,T24,T15	Yes	T8,T24,T15	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T16,T12,T24	Yes	T16,T12,T24	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T16,T24,T28	Yes	T16,T12,T24	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T16,T12,T24	Yes	T16,T12,T24	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T23,T25,T32	Yes	T8,T23,T25	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T23,T33,T34	Yes	T8,T23,T32	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T8,T23,T25	Yes	T8,T23,T25	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T26,T27,T23	Yes	T26,T27,T23	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T27,T23,T28	Yes	T27,T23,T28	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T26,T27,T23	Yes	T26,T27,T23	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T23,T28,T25	Yes	T23,T28,T25	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T25,T32,T33	Yes	T28,T25,T35	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T23,T28,T25	Yes	T23,T28,T25	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T18,T7,T8	Yes	T18,T7,T12	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T18,T7,T8	Yes	T18,T7,T8	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T3,T4,T18	Yes	T3,T4,T18	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T16,T17,T36	Yes	T16,T17,T36	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	238419330	238314488	0	0
CsrngAppIfOut_A	238419330	238314488	0	0
FpvSecCmCntAlertCheck_A	238419330	44	0	0
FpvSecCmGenCmdFifoRptrCheck_A	238419330	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	238419330	0	0	0
FpvSecCmMainFsmCheck_A	238419330	0	0	0
FpvSecCmRegWeOnehotCheck_A	238419330	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	238419330	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	238419330	0	0	0
IntrEdnCmdReqDoneKnownO_A	238419330	238314488	0	0
TlAReadyKnownO_A	238419330	238314488	0	0
TlDValidKnownO_A	238419330	238314488	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	238419330	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	238419330	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	238419330	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	238419330	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	238419330	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	238419330	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	238419330	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	238419330	501245	0	308
gen_edn_if_asserts[0].EdnDataStable_A	238419330	22383	0	426
gen_edn_if_asserts[0].EdnEndPointOut_A	238419330	238314488	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	238419330	87666	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	238419330	501245	0	308
gen_edn_if_asserts[1].EdnDataStable_A	238419330	4347	0	144
gen_edn_if_asserts[1].EdnEndPointOut_A	238419330	238314488	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	238419330	87666	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	238419330	501245	0	308
gen_edn_if_asserts[2].EdnDataStable_A	238419330	4201	0	118
gen_edn_if_asserts[2].EdnEndPointOut_A	238419330	238314488	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	238419330	87666	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	238419330	501245	0	308
gen_edn_if_asserts[3].EdnDataStable_A	238419330	2167	0	125
gen_edn_if_asserts[3].EdnEndPointOut_A	238419330	238314488	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	238419330	87666	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	238419330	501245	0	308
gen_edn_if_asserts[4].EdnDataStable_A	238419330	7010	0	107
gen_edn_if_asserts[4].EdnEndPointOut_A	238419330	238314488	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	238419330	87666	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	238419330	501245	0	308
gen_edn_if_asserts[5].EdnDataStable_A	238419330	6831	0	98
gen_edn_if_asserts[5].EdnEndPointOut_A	238419330	238314488	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	238419330	87666	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	238419330	501245	0	308
gen_edn_if_asserts[6].EdnDataStable_A	238419330	3109	0	97
gen_edn_if_asserts[6].EdnEndPointOut_A	238419330	238314488	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	238419330	87666	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	44	0	0
T6	2235	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T36	2684	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	1053	0	0	0
T45	2008	0	0	0
T46	1811	0	0	0
T47	2929	0	0	0
T48	3243	0	0	0
T49	1035	0	0	0
T50	1129	0	0	0
T51	2240	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	501245	0	308
T1	2132	591	0	0
T2	914	538	0	0
T3	2692	208	0	0
T4	3904	35	0	0
T7	6750	65	0	0
T8	2533	1326	0	2
T12	1984	903	0	2
T16	2235	523	0	0
T18	18382	2470	0	0
T19	0	0	0	2
T22	0	0	0	2
T26	1294	464	0	2
T35	0	0	0	2
T45	0	0	0	2
T46	0	0	0	2
T49	0	0	0	2
T52	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	22383	0	426
T3	2692	4	0	1
T4	3904	3	0	1
T7	6750	1095	0	1
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T17	0	4	0	1
T18	18382	10	0	0
T19	0	90	0	0
T22	2683	0	0	0
T23	0	3	0	1
T24	1982	0	0	0
T25	0	9	0	1
T26	1294	0	0	0
T28	0	51	0	1
T53	0	11	0	1
T54	0	0	0	1
T55	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87666	0	0
T1	2132	641	0	0
T2	914	335	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1082	0	0
T6	0	1126	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T44	0	7	0	0
T56	0	23	0	0
T57	0	7	0	0
T58	0	322	0	0
T59	0	1087	0	0
T60	0	592	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	501245	0	308
T1	2132	591	0	0
T2	914	538	0	0
T3	2692	208	0	0
T4	3904	35	0	0
T7	6750	65	0	0
T8	2533	1326	0	2
T12	1984	903	0	2
T16	2235	523	0	0
T18	18382	2470	0	0
T19	0	0	0	2
T22	0	0	0	2
T26	1294	464	0	2
T35	0	0	0	2
T45	0	0	0	2
T46	0	0	0	2
T49	0	0	0	2
T52	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	4347	0	144
T12	1984	1	0	0
T15	2411	0	0	0
T17	1887	0	0	0
T19	314850	0	0	0
T22	2683	4	0	0
T23	3535	3	0	1
T24	1982	0	0	0
T25	0	3	0	1
T26	1294	0	0	0
T27	3500	0	0	0
T28	0	3	0	1
T29	0	34	0	1
T30	0	1095	0	1
T31	0	0	0	1
T32	0	3	0	1
T34	0	0	0	1
T47	0	3	0	1
T53	1422	0	0	0
T61	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87666	0	0
T1	2132	641	0	0
T2	914	335	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1082	0	0
T6	0	1126	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T44	0	7	0	0
T56	0	23	0	0
T57	0	7	0	0
T58	0	322	0	0
T59	0	1087	0	0
T60	0	592	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	501245	0	308
T1	2132	591	0	0
T2	914	538	0	0
T3	2692	208	0	0
T4	3904	35	0	0
T7	6750	65	0	0
T8	2533	1326	0	2
T12	1984	903	0	2
T16	2235	523	0	0
T18	18382	2470	0	0
T19	0	0	0	2
T22	0	0	0	2
T26	1294	464	0	2
T35	0	0	0	2
T45	0	0	0	2
T46	0	0	0	2
T49	0	0	0	2
T52	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	4201	0	118
T8	2533	4	0	0
T12	1984	0	0	0
T15	2411	15	0	1
T16	2235	0	0	0
T19	314850	0	0	0
T22	2683	0	0	0
T23	0	27	0	1
T24	1982	18	0	1
T25	0	23	0	1
T26	1294	0	0	0
T27	3500	3	0	1
T28	0	61	0	1
T29	0	255	0	1
T30	0	0	0	1
T32	0	1155	0	1
T33	0	6	0	1
T53	1422	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87666	0	0
T1	2132	641	0	0
T2	914	335	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1082	0	0
T6	0	1126	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T44	0	7	0	0
T56	0	23	0	0
T57	0	7	0	0
T58	0	322	0	0
T59	0	1087	0	0
T60	0	592	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	501245	0	308
T1	2132	591	0	0
T2	914	538	0	0
T3	2692	208	0	0
T4	3904	35	0	0
T7	6750	65	0	0
T8	2533	1326	0	2
T12	1984	903	0	2
T16	2235	523	0	0
T18	18382	2470	0	0
T19	0	0	0	2
T22	0	0	0	2
T26	1294	464	0	2
T35	0	0	0	2
T45	0	0	0	2
T46	0	0	0	2
T49	0	0	0	2
T52	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	2167	0	125
T12	1984	4	0	0
T15	2411	0	0	0
T16	2235	8	0	1
T19	314850	0	0	0
T22	2683	0	0	0
T23	3535	3	0	1
T24	1982	50	0	1
T25	0	3	0	1
T26	1294	0	0	0
T27	3500	0	0	0
T28	0	60	0	1
T29	0	49	0	1
T30	0	3	0	1
T32	0	29	0	1
T47	0	19	0	1
T53	1422	0	0	0
T62	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87666	0	0
T1	2132	641	0	0
T2	914	335	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1082	0	0
T6	0	1126	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T44	0	7	0	0
T56	0	23	0	0
T57	0	7	0	0
T58	0	322	0	0
T59	0	1087	0	0
T60	0	592	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	501245	0	308
T1	2132	591	0	0
T2	914	538	0	0
T3	2692	208	0	0
T4	3904	35	0	0
T7	6750	65	0	0
T8	2533	1326	0	2
T12	1984	903	0	2
T16	2235	523	0	0
T18	18382	2470	0	0
T19	0	0	0	2
T22	0	0	0	2
T26	1294	464	0	2
T35	0	0	0	2
T45	0	0	0	2
T46	0	0	0	2
T49	0	0	0	2
T52	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	7010	0	107
T8	2533	1	0	0
T12	1984	0	0	0
T15	2411	0	0	0
T16	2235	0	0	0
T19	314850	0	0	0
T22	2683	0	0	0
T23	0	29	0	1
T24	1982	0	0	0
T25	0	3	0	1
T26	1294	0	0	0
T27	3500	0	0	0
T31	0	3	0	1
T32	0	3	0	1
T33	0	33	0	1
T34	0	31	0	1
T53	1422	0	0	0
T61	0	3	0	1
T62	0	3	0	1
T63	0	3	0	1
T64	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87666	0	0
T1	2132	641	0	0
T2	914	335	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1082	0	0
T6	0	1126	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T44	0	7	0	0
T56	0	23	0	0
T57	0	7	0	0
T58	0	322	0	0
T59	0	1087	0	0
T60	0	592	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	501245	0	308
T1	2132	591	0	0
T2	914	538	0	0
T3	2692	208	0	0
T4	3904	35	0	0
T7	6750	65	0	0
T8	2533	1326	0	2
T12	1984	903	0	2
T16	2235	523	0	0
T18	18382	2470	0	0
T19	0	0	0	2
T22	0	0	0	2
T26	1294	464	0	2
T35	0	0	0	2
T45	0	0	0	2
T46	0	0	0	2
T49	0	0	0	2
T52	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	6831	0	98
T15	2411	0	0	0
T17	1887	0	0	0
T19	314850	0	0	0
T22	2683	0	0	0
T23	3535	57	0	1
T24	1982	0	0	0
T25	0	881	0	1
T26	1294	4	0	0
T27	3500	17	0	1
T28	9170	1014	0	1
T29	0	61	0	1
T36	0	4	0	1
T53	1422	0	0	0
T61	0	56	0	1
T63	0	44	0	1
T65	0	4	0	0
T66	0	0	0	1
T67	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87666	0	0
T1	2132	641	0	0
T2	914	335	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1082	0	0
T6	0	1126	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T44	0	7	0	0
T56	0	23	0	0
T57	0	7	0	0
T58	0	322	0	0
T59	0	1087	0	0
T60	0	592	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	501245	0	308
T1	2132	591	0	0
T2	914	538	0	0
T3	2692	208	0	0
T4	3904	35	0	0
T7	6750	65	0	0
T8	2533	1326	0	2
T12	1984	903	0	2
T16	2235	523	0	0
T18	18382	2470	0	0
T19	0	0	0	2
T22	0	0	0	2
T26	1294	464	0	2
T35	0	0	0	2
T45	0	0	0	2
T46	0	0	0	2
T49	0	0	0	2
T52	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	3109	0	97
T5	2021	0	0	0
T17	1887	0	0	0
T23	3535	3	0	1
T25	7446	57	0	1
T28	9170	3	0	1
T31	0	3	0	1
T32	6890	48	0	1
T33	0	24	0	1
T35	2098	4	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T55	1309	0	0	0
T61	0	40	0	1
T67	0	3	0	1
T68	0	8	0	1
T69	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87666	0	0
T1	2132	641	0	0
T2	914	335	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1082	0	0
T6	0	1126	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T44	0	7	0	0
T56	0	23	0	0
T57	0	7	0	0
T58	0	322	0	0
T59	0	1087	0	0
T60	0	592	0	0