Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	238917256	10453116	0	0
boot_gen_cmd_rd_A	238917256	50076	0	0
boot_ins_cmd_rd_A	238917256	57536	0	0
ctrl_rd_A	238917256	50540	0	0
err_code_test_rd_A	238917256	56107	0	0
intr_enable_rd_A	238917256	55839	0	0
max_num_reqs_between_reseeds_rd_A	238917256	51220	0	0
regwen_rd_A	238917256	57832	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	10453116	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	108759	0	0
T20	0	71160	0	0
T21	0	417689	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T121	0	147772	0	0
T223	0	143748	0	0
T224	0	327584	0	0
T225	0	243356	0	0
T226	0	194363	0	0
T227	0	163051	0	0
T228	0	97753	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	50076	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	3137	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T225	0	3844	0	0
T229	0	1479	0	0
T230	0	3884	0	0
T231	0	8090	0	0
T232	0	2492	0	0
T233	0	2899	0	0
T234	0	8321	0	0
T235	0	3694	0	0
T236	0	517	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	57536	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	3518	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T225	0	4537	0	0
T229	0	1639	0	0
T230	0	4029	0	0
T231	0	9140	0	0
T232	0	2895	0	0
T233	0	3398	0	0
T234	0	9755	0	0
T235	0	4846	0	0
T236	0	444	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	50540	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	2870	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T72	0	1	0	0
T110	0	4	0	0
T123	0	2	0	0
T137	0	3	0	0
T225	0	3990	0	0
T229	0	1308	0	0
T230	0	3460	0	0
T237	0	4	0	0
T238	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	56107	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	3251	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T225	0	4176	0	0
T229	0	1568	0	0
T230	0	4024	0	0
T231	0	9219	0	0
T232	0	2807	0	0
T233	0	3035	0	0
T234	0	9883	0	0
T235	0	4290	0	0
T236	0	556	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	55839	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	3405	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T123	0	36	0	0
T126	0	87	0	0
T225	0	4286	0	0
T229	0	1555	0	0
T230	0	3645	0	0
T239	0	90	0	0
T240	0	34	0	0
T241	0	54	0	0
T242	0	17	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	51220	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	2871	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T225	0	3977	0	0
T229	0	1585	0	0
T230	0	3622	0	0
T231	0	8030	0	0
T232	0	2561	0	0
T233	0	3049	0	0
T234	0	8599	0	0
T235	0	3962	0	0
T236	0	402	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238917256	57832	0	0
T5	2021	0	0	0
T17	1887	0	0	0
T19	314850	3476	0	0
T23	3535	0	0	0
T25	7446	0	0	0
T27	3500	0	0	0
T28	9170	0	0	0
T35	2098	0	0	0
T52	1280	0	0	0
T54	3910	0	0	0
T225	0	4499	0	0
T229	0	1625	0	0
T230	0	3926	0	0
T231	0	9717	0	0
T232	0	2757	0	0
T233	0	3029	0	0
T234	0	9752	0	0
T235	0	4555	0	0
T236	0	519	0	0