Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.47	98.25	93.07	91.10	86.05	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.08	99.92	91.72	48.52	86.05	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T10

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
edn_i[1].edn_req	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
edn_i[2].edn_req	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
edn_i[3].edn_req	Yes	Yes	T10,T4,T14	Yes	T10,T4,T14	INPUT
edn_i[4].edn_req	Yes	Yes	T27,T28,T30	Yes	T27,T28,T30	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T27,T18	Yes	T2,T27,T18	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T26,T28	Yes	T3,T26,T28	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T6,T31	Yes	T1,T6,T31	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T8,T32,T33	Yes	T26,T8,T19	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T33,T11,T34	Yes	T33,T22,T11	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T35,T22,T36	Yes	T27,T28,T29	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T4,T14,T28	Yes	T4,T14,T28	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T4,T28,T22	Yes	T4,T28,T22	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T10,T4,T14	Yes	T10,T4,T14	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T27,T28,T37	Yes	T27,T28,T37	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T37,T38,T36	Yes	T27,T37,T38	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T27,T28,T37	Yes	T27,T28,T37	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T27,T18	Yes	T2,T27,T18	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T27,T11,T34	Yes	T27,T26,T28	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T27,T18	Yes	T2,T27,T18	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T3,T26,T37	Yes	T3,T26,T37	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T26,T12,T39	Yes	T26,T12,T34	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T26,T28	Yes	T3,T26,T28	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T31	Yes	T1,T31,T40	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T6	Yes	T1,T31,T27	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T10,T14	Yes	T2,T10,T14	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T40,T41	Yes	T6,T40,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	191926264	191821889	0	0
CsrngAppIfOut_A	191926264	191821889	0	0
FpvSecCmCntAlertCheck_A	191926264	43	0	0
FpvSecCmGenCmdFifoRptrCheck_A	191926264	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	191926264	0	0	0
FpvSecCmMainFsmCheck_A	191926264	0	0	0
FpvSecCmRegWeOnehotCheck_A	191926264	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	191926264	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	191926264	0	0	0
IntrEdnCmdReqDoneKnownO_A	191926264	191821889	0	0
TlAReadyKnownO_A	191926264	191821889	0	0
TlDValidKnownO_A	191926264	191821889	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	191926264	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	191926264	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	191926264	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	191926264	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	191926264	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	191926264	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	191926264	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	191926264	502809	0	316
gen_edn_if_asserts[0].EdnDataStable_A	191926264	25806	0	413
gen_edn_if_asserts[0].EdnEndPointOut_A	191926264	191821889	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	191926264	86117	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	191926264	502809	0	316
gen_edn_if_asserts[1].EdnDataStable_A	191926264	4191	0	155
gen_edn_if_asserts[1].EdnEndPointOut_A	191926264	191821889	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	191926264	86117	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	191926264	502809	0	316
gen_edn_if_asserts[2].EdnDataStable_A	191926264	6985	0	135
gen_edn_if_asserts[2].EdnEndPointOut_A	191926264	191821889	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	191926264	86117	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	191926264	502809	0	316
gen_edn_if_asserts[3].EdnDataStable_A	191926264	3065	0	127
gen_edn_if_asserts[3].EdnEndPointOut_A	191926264	191821889	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	191926264	86117	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	191926264	502809	0	316
gen_edn_if_asserts[4].EdnDataStable_A	191926264	6899	0	115
gen_edn_if_asserts[4].EdnEndPointOut_A	191926264	191821889	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	191926264	86117	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	191926264	502809	0	316
gen_edn_if_asserts[5].EdnDataStable_A	191926264	1697	0	105
gen_edn_if_asserts[5].EdnEndPointOut_A	191926264	191821889	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	191926264	86117	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	191926264	502809	0	316
gen_edn_if_asserts[6].EdnDataStable_A	191926264	3094	0	94
gen_edn_if_asserts[6].EdnEndPointOut_A	191926264	191821889	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	191926264	86117	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	43	0	0
T15	1858	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T32	1030	0	0	0
T33	2180	0	0	0
T35	3230	0	0	0
T37	2095	0	0	0
T38	2923	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	2113	0	0	0
T50	2224	0	0	0
T51	2369	0	0	0
T52	4594	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	502809	0	316
T1	2707	17	0	0
T2	2536	217	0	0
T3	2089	186	0	0
T4	2141	1094	0	0
T5	732	241	0	0
T6	14512	1149	0	0
T10	2120	405	0	0
T14	2904	191	0	0
T18	0	0	0	2
T19	0	0	0	2
T23	0	0	0	2
T24	0	0	0	2
T31	3353	16	0	0
T40	12961	2245	0	0
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	25806	0	413
T1	2707	16	0	1
T2	2536	0	0	0
T3	2089	0	0	0
T4	2141	0	0	0
T5	732	1	0	0
T6	14512	6	0	0
T10	2120	0	0	0
T14	2904	0	0	0
T26	0	33	0	1
T27	0	15	0	1
T28	0	0	0	1
T31	3353	19	0	1
T40	12961	9	0	0
T41	0	12	0	0
T59	0	4	0	1
T60	0	3	0	1
T61	0	0	0	1
T62	0	0	0	1
T63	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	86117	0	0
T4	2141	30	0	0
T5	732	31	0	0
T6	14512	0	0	0
T7	819	244	0	0
T8	0	1155	0	0
T9	0	639	0	0
T14	2904	0	0	0
T15	0	422	0	0
T18	2761	0	0	0
T27	3308	0	0	0
T30	0	390	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T41	20807	0	0	0
T64	0	621	0	0
T65	0	407	0	0
T66	0	1155	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	502809	0	316
T1	2707	17	0	0
T2	2536	217	0	0
T3	2089	186	0	0
T4	2141	1094	0	0
T5	732	241	0	0
T6	14512	1149	0	0
T10	2120	405	0	0
T14	2904	191	0	0
T18	0	0	0	2
T19	0	0	0	2
T23	0	0	0	2
T24	0	0	0	2
T31	3353	16	0	0
T40	12961	2245	0	0
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	4191	0	155
T8	2792	1	0	0
T11	0	15	0	1
T19	2228	4	0	0
T22	0	12	0	1
T26	3590	3	0	1
T28	3040	0	0	0
T30	804	0	0	0
T32	0	3	0	1
T33	0	4	0	0
T34	0	19	0	1
T36	0	3	0	1
T53	1830	0	0	0
T60	1303	0	0	0
T61	1582	0	0	0
T62	1102	0	0	0
T63	1084	0	0	0
T67	0	4	0	1
T68	0	0	0	1
T69	0	0	0	1
T70	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	86117	0	0
T4	2141	30	0	0
T5	732	31	0	0
T6	14512	0	0	0
T7	819	244	0	0
T8	0	1155	0	0
T9	0	639	0	0
T14	2904	0	0	0
T15	0	422	0	0
T18	2761	0	0	0
T27	3308	0	0	0
T30	0	390	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T41	20807	0	0	0
T64	0	621	0	0
T65	0	407	0	0
T66	0	1155	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	502809	0	316
T1	2707	17	0	0
T2	2536	217	0	0
T3	2089	186	0	0
T4	2141	1094	0	0
T5	732	241	0	0
T6	14512	1149	0	0
T10	2120	405	0	0
T14	2904	191	0	0
T18	0	0	0	2
T19	0	0	0	2
T23	0	0	0	2
T24	0	0	0	2
T31	3353	16	0	0
T40	12961	2245	0	0
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	6985	0	135
T8	2792	0	0	0
T11	0	3	0	1
T18	2761	0	0	0
T22	0	1112	0	1
T26	3590	0	0	0
T27	3308	3	0	1
T28	3040	4	0	1
T29	0	3	0	1
T33	0	4	0	1
T35	0	42	0	1
T38	0	7	0	1
T41	20807	0	0	0
T51	0	4	0	1
T59	1660	0	0	0
T60	1303	0	0	0
T61	1582	0	0	0
T62	1102	0	0	0
T71	0	4	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	86117	0	0
T4	2141	30	0	0
T5	732	31	0	0
T6	14512	0	0	0
T7	819	244	0	0
T8	0	1155	0	0
T9	0	639	0	0
T14	2904	0	0	0
T15	0	422	0	0
T18	2761	0	0	0
T27	3308	0	0	0
T30	0	390	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T41	20807	0	0	0
T64	0	621	0	0
T65	0	407	0	0
T66	0	1155	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	502809	0	316
T1	2707	17	0	0
T2	2536	217	0	0
T3	2089	186	0	0
T4	2141	1094	0	0
T5	732	241	0	0
T6	14512	1149	0	0
T10	2120	405	0	0
T14	2904	191	0	0
T18	0	0	0	2
T19	0	0	0	2
T23	0	0	0	2
T24	0	0	0	2
T31	3353	16	0	0
T40	12961	2245	0	0
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	3065	0	127
T4	2141	1	0	0
T5	732	0	0	0
T6	14512	0	0	0
T7	819	0	0	0
T10	2120	4	0	1
T11	0	3	0	1
T12	0	12	0	1
T14	2904	4	0	1
T22	0	54	0	1
T27	3308	0	0	0
T28	0	35	0	1
T31	3353	0	0	0
T34	0	34	0	1
T36	0	0	0	1
T38	0	3	0	1
T40	12961	0	0	0
T41	20807	0	0	0
T55	0	4	0	0
T72	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	86117	0	0
T4	2141	30	0	0
T5	732	31	0	0
T6	14512	0	0	0
T7	819	244	0	0
T8	0	1155	0	0
T9	0	639	0	0
T14	2904	0	0	0
T15	0	422	0	0
T18	2761	0	0	0
T27	3308	0	0	0
T30	0	390	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T41	20807	0	0	0
T64	0	621	0	0
T65	0	407	0	0
T66	0	1155	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	502809	0	316
T1	2707	17	0	0
T2	2536	217	0	0
T3	2089	186	0	0
T4	2141	1094	0	0
T5	732	241	0	0
T6	14512	1149	0	0
T10	2120	405	0	0
T14	2904	191	0	0
T18	0	0	0	2
T19	0	0	0	2
T23	0	0	0	2
T24	0	0	0	2
T31	3353	16	0	0
T40	12961	2245	0	0
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	6899	0	115
T8	2792	0	0	0
T11	0	3	0	1
T18	2761	0	0	0
T26	3590	0	0	0
T27	3308	3	0	1
T28	3040	3	0	1
T36	0	36	0	1
T37	0	4	0	0
T38	0	33	0	1
T41	20807	0	0	0
T55	0	1	0	0
T59	1660	0	0	0
T60	1303	0	0	0
T61	1582	0	0	0
T62	1102	0	0	0
T73	0	4	0	1
T74	0	3	0	1
T75	0	4	0	1
T76	0	0	0	1
T77	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	86117	0	0
T4	2141	30	0	0
T5	732	31	0	0
T6	14512	0	0	0
T7	819	244	0	0
T8	0	1155	0	0
T9	0	639	0	0
T14	2904	0	0	0
T15	0	422	0	0
T18	2761	0	0	0
T27	3308	0	0	0
T30	0	390	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T41	20807	0	0	0
T64	0	621	0	0
T65	0	407	0	0
T66	0	1155	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	502809	0	316
T1	2707	17	0	0
T2	2536	217	0	0
T3	2089	186	0	0
T4	2141	1094	0	0
T5	732	241	0	0
T6	14512	1149	0	0
T10	2120	405	0	0
T14	2904	191	0	0
T18	0	0	0	2
T19	0	0	0	2
T23	0	0	0	2
T24	0	0	0	2
T31	3353	16	0	0
T40	12961	2245	0	0
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	1697	0	105
T2	2536	4	0	1
T3	2089	0	0	0
T4	2141	0	0	0
T5	732	0	0	0
T6	14512	0	0	0
T7	819	0	0	0
T10	2120	0	0	0
T11	0	13	0	1
T14	2904	0	0	0
T18	0	4	0	0
T26	0	3	0	1
T27	0	49	0	1
T28	0	3	0	1
T31	3353	0	0	0
T34	0	23	0	1
T36	0	40	0	1
T38	0	3	0	1
T40	12961	0	0	0
T68	0	3	0	1
T78	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	86117	0	0
T4	2141	30	0	0
T5	732	31	0	0
T6	14512	0	0	0
T7	819	244	0	0
T8	0	1155	0	0
T9	0	639	0	0
T14	2904	0	0	0
T15	0	422	0	0
T18	2761	0	0	0
T27	3308	0	0	0
T30	0	390	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T41	20807	0	0	0
T64	0	621	0	0
T65	0	407	0	0
T66	0	1155	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	502809	0	316
T1	2707	17	0	0
T2	2536	217	0	0
T3	2089	186	0	0
T4	2141	1094	0	0
T5	732	241	0	0
T6	14512	1149	0	0
T10	2120	405	0	0
T14	2904	191	0	0
T18	0	0	0	2
T19	0	0	0	2
T23	0	0	0	2
T24	0	0	0	2
T31	3353	16	0	0
T40	12961	2245	0	0
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	3094	0	94
T3	2089	8	0	1
T4	2141	0	0	0
T5	732	0	0	0
T6	14512	0	0	0
T7	819	0	0	0
T10	2120	0	0	0
T11	0	3	0	1
T12	0	15	0	1
T14	2904	0	0	0
T26	0	14	0	1
T27	3308	0	0	0
T28	0	3	0	1
T31	3353	0	0	0
T34	0	15	0	1
T37	0	4	0	1
T38	0	3	0	1
T40	12961	0	0	0
T74	0	0	0	1
T79	0	3	0	1
T80	0	4	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	86117	0	0
T4	2141	30	0	0
T5	732	31	0	0
T6	14512	0	0	0
T7	819	244	0	0
T8	0	1155	0	0
T9	0	639	0	0
T14	2904	0	0	0
T15	0	422	0	0
T18	2761	0	0	0
T27	3308	0	0	0
T30	0	390	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T41	20807	0	0	0
T64	0	621	0	0
T65	0	407	0	0
T66	0	1155	0	0