Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	192456502	9031475	0	0
boot_gen_cmd_rd_A	192456502	33110	0	0
boot_ins_cmd_rd_A	192456502	38504	0	0
ctrl_rd_A	192456502	34035	0	0
err_code_test_rd_A	192456502	37582	0	0
intr_enable_rd_A	192456502	38368	0	0
max_num_reqs_between_reseeds_rd_A	192456502	34869	0	0
regwen_rd_A	192456502	40101	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	9031475	0	0
T20	2361	0	0	0
T23	162209	65646	0	0
T24	0	128733	0	0
T25	0	72310	0	0
T68	2617	0	0	0
T69	3217	0	0	0
T78	1758	0	0	0
T79	1318	0	0	0
T99	2699	0	0	0
T124	1818	0	0	0
T167	2233	0	0	0
T180	1510	0	0	0
T223	0	96158	0	0
T224	0	262324	0	0
T225	0	280652	0	0
T226	0	430731	0	0
T227	0	180980	0	0
T228	0	308645	0	0
T229	0	24112	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	33110	0	0
T148	1283	0	0	0
T154	525	0	0	0
T200	443	0	0	0
T230	411031	2408	0	0
T231	0	2300	0	0
T232	0	1449	0	0
T233	0	1305	0	0
T234	0	4050	0	0
T235	0	6457	0	0
T236	0	3872	0	0
T237	0	536	0	0
T238	0	6649	0	0
T239	0	3544	0	0
T240	1484	0	0	0
T241	588	0	0	0
T242	2690	0	0	0
T243	3779	0	0	0
T244	2492	0	0	0
T245	1571	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	38504	0	0
T148	1283	0	0	0
T154	525	0	0	0
T200	443	0	0	0
T230	411031	2711	0	0
T231	0	2637	0	0
T232	0	1655	0	0
T233	0	1673	0	0
T234	0	4516	0	0
T235	0	7381	0	0
T236	0	4407	0	0
T237	0	530	0	0
T238	0	8291	0	0
T239	0	4154	0	0
T240	1484	0	0	0
T241	588	0	0	0
T242	2690	0	0	0
T243	3779	0	0	0
T244	2492	0	0	0
T245	1571	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	34035	0	0
T9	1740	0	0	0
T35	3230	0	0	0
T38	2923	0	0	0
T50	2224	4	0	0
T51	2369	0	0	0
T52	4594	0	0	0
T54	1145	0	0	0
T64	1758	0	0	0
T81	0	4	0	0
T146	2481	0	0	0
T175	0	1	0	0
T183	2438	0	0	0
T219	0	3	0	0
T230	0	2043	0	0
T231	0	2321	0	0
T232	0	1525	0	0
T233	0	1576	0	0
T246	0	5	0	0
T247	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	37582	0	0
T148	1283	0	0	0
T154	525	0	0	0
T200	443	0	0	0
T230	411031	2884	0	0
T231	0	2310	0	0
T232	0	1450	0	0
T233	0	1646	0	0
T234	0	4639	0	0
T235	0	7019	0	0
T236	0	4530	0	0
T237	0	626	0	0
T238	0	7960	0	0
T239	0	3983	0	0
T240	1484	0	0	0
T241	588	0	0	0
T242	2690	0	0	0
T243	3779	0	0	0
T244	2492	0	0	0
T245	1571	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	38368	0	0
T16	1291	0	0	0
T17	735	0	0	0
T42	1769	0	0	0
T56	1421	0	0	0
T80	1670	0	0	0
T115	2413	0	0	0
T139	2375	0	0	0
T145	916	0	0	0
T175	26591	81	0	0
T177	0	15	0	0
T214	1783	0	0	0
T230	0	2611	0	0
T231	0	2183	0	0
T232	0	1821	0	0
T233	0	1844	0	0
T248	0	24	0	0
T249	0	26	0	0
T250	0	15	0	0
T251	0	59	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	34869	0	0
T148	1283	0	0	0
T154	525	0	0	0
T200	443	0	0	0
T230	411031	2315	0	0
T231	0	2060	0	0
T232	0	1459	0	0
T233	0	1261	0	0
T234	0	3907	0	0
T235	0	6656	0	0
T236	0	4064	0	0
T237	0	528	0	0
T238	0	7178	0	0
T239	0	3607	0	0
T240	1484	0	0	0
T241	588	0	0	0
T242	2690	0	0	0
T243	3779	0	0	0
T244	2492	0	0	0
T245	1571	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192456502	40101	0	0
T148	1283	0	0	0
T154	525	0	0	0
T200	443	0	0	0
T230	411031	2774	0	0
T231	0	2713	0	0
T232	0	1761	0	0
T233	0	1498	0	0
T234	0	4520	0	0
T235	0	7502	0	0
T236	0	4390	0	0
T237	0	752	0	0
T238	0	8047	0	0
T239	0	4228	0	0
T240	1484	0	0	0
T241	588	0	0	0
T242	2690	0	0	0
T243	3779	0	0	0
T244	2492	0	0	0
T245	1571	0	0	0