Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	98.25	93.07	90.85	86.63	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	86.94	99.92	91.72	47.04	86.63	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T18,T12

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T4,T19

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T20,T21	Yes	T5,T20,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T7,T22	Yes	T1,T7,T22	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T4,T23	Yes	T2,T4,T23	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T7,T23	Yes	T1,T7,T23	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	INPUT
edn_i[4].edn_req	Yes	Yes	T7,T23,T24	Yes	T7,T23,T24	INPUT
edn_i[5].edn_req	Yes	Yes	T23,T24,T12	Yes	T23,T24,T12	INPUT
edn_i[6].edn_req	Yes	Yes	T7,T23,T25	Yes	T7,T23,T25	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T7,T22	Yes	T1,T7,T22	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T22,T23	Yes	T1,T22,T23	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T7,T22	Yes	T1,T7,T22	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T23,T24	Yes	T2,T23,T24	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T26,T27,T28	Yes	T24,T26,T27	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T24,T29	Yes	T23,T24,T29	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T23,T25	Yes	T1,T7,T23	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T23,T30	Yes	T1,T7,T23	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T7,T23	Yes	T1,T7,T23	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T22,T23,T31	Yes	T3,T22,T23	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T22,T31,T25	Yes	T3,T22,T23	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T7,T23,T24	Yes	T7,T23,T24	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T7,T24,T32	Yes	T7,T24,T32	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T7,T23,T24	Yes	T7,T23,T24	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T23,T24,T12	Yes	T23,T24,T12	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T24,T33,T34	Yes	T23,T24,T33	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T23,T24,T12	Yes	T23,T24,T12	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T7,T23,T25	Yes	T7,T23,T25	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T7,T23,T25	Yes	T7,T23,T25	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T7,T23,T25	Yes	T7,T23,T25	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T7,T22	Yes	T1,T7,T22	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T7,T22	Yes	T1,T7,T22	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T18,T38	Yes	T3,T18,T38	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T4,T38	Yes	T2,T4,T38	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T18,T38	Yes	T3,T18,T38	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T4,T38	Yes	T2,T4,T38	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T20,T39	Yes	T5,T20,T39	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T19,T20	Yes	T5,T19,T20	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	217704587	217600457	0	0
CsrngAppIfOut_A	217704587	217600457	0	0
FpvSecCmCntAlertCheck_A	217704587	43	0	0
FpvSecCmGenCmdFifoRptrCheck_A	217704587	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	217704587	0	0	0
FpvSecCmMainFsmCheck_A	217704587	0	0	0
FpvSecCmRegWeOnehotCheck_A	217704587	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	217704587	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	217704587	0	0	0
IntrEdnCmdReqDoneKnownO_A	217704587	217600457	0	0
TlAReadyKnownO_A	217704587	217600457	0	0
TlDValidKnownO_A	217704587	217600457	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	217704587	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	217704587	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	217704587	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	217704587	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	217704587	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	217704587	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	217704587	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	217704587	493330	0	312
gen_edn_if_asserts[0].EdnDataStable_A	217704587	22451	0	448
gen_edn_if_asserts[0].EdnEndPointOut_A	217704587	217600457	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	217704587	90336	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	217704587	493330	0	312
gen_edn_if_asserts[1].EdnDataStable_A	217704587	6762	0	117
gen_edn_if_asserts[1].EdnEndPointOut_A	217704587	217600457	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	217704587	90336	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	217704587	493330	0	312
gen_edn_if_asserts[2].EdnDataStable_A	217704587	4461	0	107
gen_edn_if_asserts[2].EdnEndPointOut_A	217704587	217600457	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	217704587	90336	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	217704587	493330	0	312
gen_edn_if_asserts[3].EdnDataStable_A	217704587	3265	0	93
gen_edn_if_asserts[3].EdnEndPointOut_A	217704587	217600457	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	217704587	90336	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	217704587	493330	0	312
gen_edn_if_asserts[4].EdnDataStable_A	217704587	51131	0	91
gen_edn_if_asserts[4].EdnEndPointOut_A	217704587	217600457	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	217704587	90336	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	217704587	493330	0	312
gen_edn_if_asserts[5].EdnDataStable_A	217704587	2067	0	82
gen_edn_if_asserts[5].EdnEndPointOut_A	217704587	217600457	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	217704587	90336	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	217704587	493330	0	312
gen_edn_if_asserts[6].EdnDataStable_A	217704587	2661	0	82
gen_edn_if_asserts[6].EdnEndPointOut_A	217704587	217600457	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	217704587	90336	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	43	0	0
T4	1836	1	0	0
T7	5698	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	1813	0	0	0
T49	1670	0	0	0
T50	1372	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	493330	0	312
T1	2080	35	0	0
T2	1616	952	0	0
T3	2798	557	0	0
T4	1836	1115	0	0
T5	0	0	0	2
T7	5698	63	0	0
T15	0	0	0	2
T18	1396	131	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	1989	16	0	0
T23	3154	55	0	0
T38	1656	1579	0	2
T39	0	0	0	2
T40	1070	14	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	22451	0	448
T1	2080	57	0	1
T2	1616	0	0	0
T3	2798	0	0	0
T4	1836	0	0	0
T7	5698	3	0	1
T11	0	15	0	1
T18	1396	4	0	1
T22	1989	36	0	1
T23	3154	56	0	1
T38	1656	0	0	0
T40	1070	3	0	1
T48	0	54	0	1
T49	0	3	0	1
T54	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	90336	0	0
T2	1616	648	0	0
T3	2798	0	0	0
T4	1836	1064	0	0
T6	0	362	0	0
T7	5698	0	0	0
T13	0	770	0	0
T14	0	841	0	0
T18	1396	0	0	0
T19	0	26	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	318	0	0
T42	0	804	0	0
T48	1813	0	0	0
T55	0	508	0	0
T56	0	902	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	493330	0	312
T1	2080	35	0	0
T2	1616	952	0	0
T3	2798	557	0	0
T4	1836	1115	0	0
T5	0	0	0	2
T7	5698	63	0	0
T15	0	0	0	2
T18	1396	131	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	1989	16	0	0
T23	3154	55	0	0
T38	1656	1579	0	2
T39	0	0	0	2
T40	1070	14	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	6762	0	117
T5	191141	0	0	0
T11	1904	0	0	0
T23	3154	3	0	1
T24	2037	3	0	1
T26	0	54	0	1
T27	0	891	0	1
T28	0	583	0	1
T29	0	3	0	1
T40	1070	0	0	0
T48	1813	0	0	0
T49	1670	0	0	0
T50	1372	0	0	0
T54	1833	0	0	0
T57	0	4	0	0
T58	0	3	0	1
T59	0	3	0	1
T60	0	31	0	1
T61	1322	0	0	0
T62	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	90336	0	0
T2	1616	648	0	0
T3	2798	0	0	0
T4	1836	1064	0	0
T6	0	362	0	0
T7	5698	0	0	0
T13	0	770	0	0
T14	0	841	0	0
T18	1396	0	0	0
T19	0	26	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	318	0	0
T42	0	804	0	0
T48	1813	0	0	0
T55	0	508	0	0
T56	0	902	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	493330	0	312
T1	2080	35	0	0
T2	1616	952	0	0
T3	2798	557	0	0
T4	1836	1115	0	0
T5	0	0	0	2
T7	5698	63	0	0
T15	0	0	0	2
T18	1396	131	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	1989	16	0	0
T23	3154	55	0	0
T38	1656	1579	0	2
T39	0	0	0	2
T40	1070	14	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	4461	0	107
T1	2080	66	0	1
T2	1616	0	0	0
T3	2798	0	0	0
T4	1836	0	0	0
T7	5698	3	0	1
T15	0	5	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	22	0	1
T24	0	3	0	1
T25	0	3	0	1
T28	0	0	0	1
T29	0	3	0	1
T30	0	23	0	1
T34	0	11	0	1
T38	1656	0	0	0
T40	1070	0	0	0
T63	0	50	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	90336	0	0
T2	1616	648	0	0
T3	2798	0	0	0
T4	1836	1064	0	0
T6	0	362	0	0
T7	5698	0	0	0
T13	0	770	0	0
T14	0	841	0	0
T18	1396	0	0	0
T19	0	26	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	318	0	0
T42	0	804	0	0
T48	1813	0	0	0
T55	0	508	0	0
T56	0	902	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	493330	0	312
T1	2080	35	0	0
T2	1616	952	0	0
T3	2798	557	0	0
T4	1836	1115	0	0
T5	0	0	0	2
T7	5698	63	0	0
T15	0	0	0	2
T18	1396	131	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	1989	16	0	0
T23	3154	55	0	0
T38	1656	1579	0	2
T39	0	0	0	2
T40	1070	14	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	3265	0	93
T3	2798	4	0	1
T4	1836	0	0	0
T7	5698	0	0	0
T16	0	3	0	1
T18	1396	0	0	0
T22	1989	58	0	1
T23	3154	3	0	1
T25	0	18	0	1
T26	0	3	0	1
T28	0	3	0	1
T29	0	3	0	1
T30	0	70	0	1
T31	0	19	0	1
T38	1656	0	0	0
T40	1070	0	0	0
T48	1813	0	0	0
T49	1670	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	90336	0	0
T2	1616	648	0	0
T3	2798	0	0	0
T4	1836	1064	0	0
T6	0	362	0	0
T7	5698	0	0	0
T13	0	770	0	0
T14	0	841	0	0
T18	1396	0	0	0
T19	0	26	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	318	0	0
T42	0	804	0	0
T48	1813	0	0	0
T55	0	508	0	0
T56	0	902	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	493330	0	312
T1	2080	35	0	0
T2	1616	952	0	0
T3	2798	557	0	0
T4	1836	1115	0	0
T5	0	0	0	2
T7	5698	63	0	0
T15	0	0	0	2
T18	1396	131	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	1989	16	0	0
T23	3154	55	0	0
T38	1656	1579	0	2
T39	0	0	0	2
T40	1070	14	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	51131	0	91
T7	5698	25	0	1
T11	1904	0	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	7	0	1
T24	0	34	0	1
T30	0	3	0	1
T31	0	3	0	1
T32	0	59	0	1
T34	0	18	0	1
T38	1656	0	0	0
T40	1070	0	0	0
T48	1813	0	0	0
T49	1670	0	0	0
T50	1372	0	0	0
T57	0	4	0	1
T64	0	4	0	1
T65	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	90336	0	0
T2	1616	648	0	0
T3	2798	0	0	0
T4	1836	1064	0	0
T6	0	362	0	0
T7	5698	0	0	0
T13	0	770	0	0
T14	0	841	0	0
T18	1396	0	0	0
T19	0	26	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	318	0	0
T42	0	804	0	0
T48	1813	0	0	0
T55	0	508	0	0
T56	0	902	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	493330	0	312
T1	2080	35	0	0
T2	1616	952	0	0
T3	2798	557	0	0
T4	1836	1115	0	0
T5	0	0	0	2
T7	5698	63	0	0
T15	0	0	0	2
T18	1396	131	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	1989	16	0	0
T23	3154	55	0	0
T38	1656	1579	0	2
T39	0	0	0	2
T40	1070	14	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	2067	0	82
T5	191141	0	0	0
T11	1904	0	0	0
T12	0	4	0	1
T23	3154	3	0	1
T24	2037	32	0	1
T29	0	3	0	1
T33	0	4	0	0
T34	0	41	0	1
T37	0	4	0	1
T40	1070	0	0	0
T48	1813	0	0	0
T49	1670	0	0	0
T50	1372	0	0	0
T54	1833	0	0	0
T59	0	15	0	1
T61	1322	0	0	0
T62	0	11	0	1
T66	0	4	0	1
T67	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	90336	0	0
T2	1616	648	0	0
T3	2798	0	0	0
T4	1836	1064	0	0
T6	0	362	0	0
T7	5698	0	0	0
T13	0	770	0	0
T14	0	841	0	0
T18	1396	0	0	0
T19	0	26	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	318	0	0
T42	0	804	0	0
T48	1813	0	0	0
T55	0	508	0	0
T56	0	902	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	493330	0	312
T1	2080	35	0	0
T2	1616	952	0	0
T3	2798	557	0	0
T4	1836	1115	0	0
T5	0	0	0	2
T7	5698	63	0	0
T15	0	0	0	2
T18	1396	131	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	1989	16	0	0
T23	3154	55	0	0
T38	1656	1579	0	2
T39	0	0	0	2
T40	1070	14	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	2661	0	82
T7	5698	927	0	1
T11	1904	0	0	0
T16	0	15	0	1
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	63	0	1
T25	0	37	0	1
T26	0	3	0	1
T29	0	39	0	1
T38	1656	0	0	0
T40	1070	0	0	0
T42	0	1	0	0
T48	1813	0	0	0
T49	1670	0	0	0
T50	1372	0	0	0
T59	0	53	0	1
T68	0	4	0	1
T69	0	34	0	1
T70	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	90336	0	0
T2	1616	648	0	0
T3	2798	0	0	0
T4	1836	1064	0	0
T6	0	362	0	0
T7	5698	0	0	0
T13	0	770	0	0
T14	0	841	0	0
T18	1396	0	0	0
T19	0	26	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	318	0	0
T42	0	804	0	0
T48	1813	0	0	0
T55	0	508	0	0
T56	0	902	0	0