Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218158621	9861289	0	0
boot_gen_cmd_rd_A	218158621	52412	0	0
boot_ins_cmd_rd_A	218158621	57528	0	0
ctrl_rd_A	218158621	51041	0	0
err_code_test_rd_A	218158621	58738	0	0
intr_enable_rd_A	218158621	57433	0	0
max_num_reqs_between_reseeds_rd_A	218158621	50755	0	0
regwen_rd_A	218158621	57929	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	9861289	0	0
T5	191141	106987	0	0
T12	2640	0	0	0
T19	737	0	0	0
T20	152596	82078	0	0
T21	0	394154	0	0
T25	2700	0	0	0
T31	4394	0	0	0
T32	3944	0	0	0
T51	1267	0	0	0
T61	1322	0	0	0
T87	1247	0	0	0
T89	0	190875	0	0
T90	0	214915	0	0
T91	0	377674	0	0
T123	0	285431	0	0
T217	0	64480	0	0
T218	0	204565	0	0
T219	0	65090	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	52412	0	0
T69	2816	0	0	0
T70	2887	0	0	0
T90	511252	0	0	0
T91	0	11448	0	0
T92	2345	0	0	0
T125	1628	0	0	0
T173	1934	0	0	0
T218	547790	3339	0	0
T219	0	2046	0	0
T220	0	737	0	0
T221	0	999	0	0
T222	0	4424	0	0
T223	0	6762	0	0
T224	0	3079	0	0
T225	0	7652	0	0
T226	0	4632	0	0
T227	1785	0	0	0
T228	30359	0	0	0
T229	2432	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	57528	0	0
T69	2816	0	0	0
T70	2887	0	0	0
T90	511252	0	0	0
T91	0	12765	0	0
T92	2345	0	0	0
T125	1628	0	0	0
T173	1934	0	0	0
T218	547790	3557	0	0
T219	0	2041	0	0
T220	0	675	0	0
T221	0	1196	0	0
T222	0	4372	0	0
T223	0	7408	0	0
T224	0	3390	0	0
T225	0	8590	0	0
T226	0	5185	0	0
T227	1785	0	0	0
T228	30359	0	0	0
T229	2432	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	51041	0	0
T69	2816	0	0	0
T70	2887	0	0	0
T90	511252	0	0	0
T91	0	10902	0	0
T92	2345	0	0	0
T125	1628	0	0	0
T166	0	3	0	0
T173	1934	0	0	0
T218	547790	3316	0	0
T219	0	1921	0	0
T220	0	709	0	0
T221	0	1100	0	0
T222	0	4111	0	0
T227	1785	0	0	0
T228	30359	0	0	0
T229	2432	0	0	0
T230	0	3	0	0
T231	0	3	0	0
T232	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	58738	0	0
T69	2816	0	0	0
T70	2887	0	0	0
T90	511252	0	0	0
T91	0	13341	0	0
T92	2345	0	0	0
T125	1628	0	0	0
T173	1934	0	0	0
T218	547790	3800	0	0
T219	0	2183	0	0
T220	0	800	0	0
T221	0	1006	0	0
T222	0	4850	0	0
T223	0	7554	0	0
T224	0	3457	0	0
T225	0	8637	0	0
T226	0	4927	0	0
T227	1785	0	0	0
T228	30359	0	0	0
T229	2432	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	57433	0	0
T69	2816	0	0	0
T70	2887	0	0	0
T90	511252	0	0	0
T91	0	11115	0	0
T92	2345	0	0	0
T125	1628	0	0	0
T173	1934	0	0	0
T218	547790	3251	0	0
T219	0	2193	0	0
T220	0	1391	0	0
T221	0	1407	0	0
T222	0	4406	0	0
T227	1785	0	0	0
T228	30359	0	0	0
T229	2432	0	0	0
T231	0	93	0	0
T233	0	8	0	0
T234	0	16	0	0
T235	0	80	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	50755	0	0
T69	2816	0	0	0
T70	2887	0	0	0
T90	511252	0	0	0
T91	0	10722	0	0
T92	2345	0	0	0
T125	1628	0	0	0
T173	1934	0	0	0
T218	547790	3080	0	0
T219	0	2103	0	0
T220	0	740	0	0
T221	0	959	0	0
T222	0	4011	0	0
T223	0	6614	0	0
T224	0	3053	0	0
T225	0	7498	0	0
T226	0	4579	0	0
T227	1785	0	0	0
T228	30359	0	0	0
T229	2432	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218158621	57929	0	0
T69	2816	0	0	0
T70	2887	0	0	0
T90	511252	0	0	0
T91	0	12427	0	0
T92	2345	0	0	0
T125	1628	0	0	0
T173	1934	0	0	0
T218	547790	3379	0	0
T219	0	2131	0	0
T220	0	707	0	0
T221	0	1265	0	0
T222	0	4490	0	0
T223	0	7567	0	0
T224	0	3637	0	0
T225	0	8302	0	0
T226	0	5296	0	0
T227	1785	0	0	0
T228	30359	0	0	0
T229	2432	0	0	0