Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.62	98.25	93.07	90.85	87.21	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.03	99.92	91.72	47.04	87.21	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T19

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T20

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T19	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T21,T22	Yes	T1,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T16,T8,T23	Yes	T16,T8,T23	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T14,T8	Yes	T3,T14,T8	INPUT
edn_i[3].edn_req	Yes	Yes	T24,T8,T23	Yes	T24,T8,T23	INPUT
edn_i[4].edn_req	Yes	Yes	T25,T16,T8	Yes	T25,T16,T8	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T16,T23	Yes	T4,T16,T23	INPUT
edn_i[6].edn_req	Yes	Yes	T23,T26,T27	Yes	T23,T26,T27	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T28	Yes	T1,T2,T28	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T16,T23,T29	Yes	T16,T8,T23	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T16,T30,T31	Yes	T16,T8,T23	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T16,T8,T23	Yes	T16,T8,T23	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T8,T32	Yes	T3,T8,T27	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T8,T32,T33	Yes	T3,T14,T8	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T14,T8	Yes	T3,T14,T8	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T8,T23,T27	Yes	T24,T8,T23	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T8,T23,T34	Yes	T8,T23,T34	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T24,T8,T23	Yes	T24,T8,T23	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T16,T8	Yes	T25,T16,T8	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T8,T35,T33	Yes	T16,T8,T35	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T25,T16,T8	Yes	T25,T16,T8	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T16,T23,T27	Yes	T16,T23,T27	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T35,T36,T37	Yes	T16,T23,T27	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T16,T23,T27	Yes	T16,T23,T27	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T23,T26,T27	Yes	T23,T26,T27	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T36,T38,T39	Yes	T23,T35,T36	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T23,T26,T27	Yes	T23,T26,T27	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T40	Yes	T1,T28,T41	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T16	Yes	T1,T41,T42	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T19,T15,T11	Yes	T19,T15,T11	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T19	Yes	T2,T3,T19	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T20	Yes	T4,T5,T20	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T19	Yes	T2,T3,T19	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T20	Yes	T4,T5,T20	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T21,T43	Yes	T1,T21,T43	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T5,T20	Yes	T1,T5,T20	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	244663004	244559612	0	0
CsrngAppIfOut_A	244663004	244559612	0	0
FpvSecCmCntAlertCheck_A	244663004	36	0	0
FpvSecCmGenCmdFifoRptrCheck_A	244663004	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	244663004	0	0	0
FpvSecCmMainFsmCheck_A	244663004	0	0	0
FpvSecCmRegWeOnehotCheck_A	244663004	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	244663004	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	244663004	0	0	0
IntrEdnCmdReqDoneKnownO_A	244663004	244559612	0	0
TlAReadyKnownO_A	244663004	244559612	0	0
TlDValidKnownO_A	244663004	244559612	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	244663004	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	244663004	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	244663004	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	244663004	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	244663004	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	244663004	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	244663004	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	244663004	476095	0	312
gen_edn_if_asserts[0].EdnDataStable_A	244663004	74126	0	419
gen_edn_if_asserts[0].EdnEndPointOut_A	244663004	244559612	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	244663004	80749	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	244663004	476095	0	312
gen_edn_if_asserts[1].EdnDataStable_A	244663004	5965	0	128
gen_edn_if_asserts[1].EdnEndPointOut_A	244663004	244559612	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	244663004	80749	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	244663004	476095	0	312
gen_edn_if_asserts[2].EdnDataStable_A	244663004	3102	0	120
gen_edn_if_asserts[2].EdnEndPointOut_A	244663004	244559612	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	244663004	80749	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	244663004	476095	0	312
gen_edn_if_asserts[3].EdnDataStable_A	244663004	3331	0	109
gen_edn_if_asserts[3].EdnEndPointOut_A	244663004	244559612	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	244663004	80749	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	244663004	476095	0	312
gen_edn_if_asserts[4].EdnDataStable_A	244663004	3283	0	101
gen_edn_if_asserts[4].EdnEndPointOut_A	244663004	244559612	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	244663004	80749	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	244663004	476095	0	312
gen_edn_if_asserts[5].EdnDataStable_A	244663004	2434	0	72
gen_edn_if_asserts[5].EdnEndPointOut_A	244663004	244559612	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	244663004	80749	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	244663004	476095	0	312
gen_edn_if_asserts[6].EdnDataStable_A	244663004	2622	0	80
gen_edn_if_asserts[6].EdnEndPointOut_A	244663004	244559612	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	244663004	80749	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	36	0	0
T7	3325	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	2270	0	0	0
T53	1813	0	0	0
T54	1710	0	0	0
T55	10641	0	0	0
T56	1794	0	0	0
T57	1157	0	0	0
T58	2479	0	0	0
T59	2479	0	0	0
T60	1228	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	476095	0	312
T1	800595	2764	0	2
T2	2228	273	0	0
T3	1833	137	0	0
T4	2344	1479	0	0
T14	2652	345	0	0
T19	1943	230	0	0
T21	0	0	0	2
T25	1054	74	0	0
T28	2508	202	0	0
T41	2630	176	0	0
T44	1440	28	0	0
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	74126	0	419
T1	800595	131	0	0
T2	2228	8	0	1
T3	1833	0	0	0
T4	2344	0	0	0
T5	0	1	0	0
T11	0	0	0	1
T14	2652	0	0	0
T15	0	4	0	1
T16	0	0	0	1
T19	1943	4	0	1
T25	1054	0	0	0
T28	2508	8	0	1
T40	0	0	0	1
T41	2630	4	0	1
T42	0	19	0	1
T44	1440	3	0	1
T69	0	4	0	0

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80749	0	0
T4	2344	1109	0	0
T5	1279	20	0	0
T6	0	762	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1110	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	352	0	0
T71	0	1142	0	0
T72	0	599	0	0
T73	0	558	0	0
T74	0	360	0	0
T75	0	19	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	476095	0	312
T1	800595	2764	0	2
T2	2228	273	0	0
T3	1833	137	0	0
T4	2344	1479	0	0
T14	2652	345	0	0
T19	1943	230	0	0
T21	0	0	0	2
T25	1054	74	0	0
T28	2508	202	0	0
T41	2630	176	0	0
T44	1440	28	0	0
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	5965	0	128
T8	2986	3	0	1
T16	8523	1070	0	1
T20	2077	0	0	0
T23	1210	3	0	1
T26	2051	0	0	0
T27	0	3	0	1
T29	0	4	0	1
T32	0	3	0	1
T35	0	3	0	1
T61	1165	0	0	0
T76	0	12	0	1
T77	0	4	0	1
T78	0	3	0	1
T79	2158	0	0	0
T80	2212	0	0	0
T81	822	0	0	0
T82	2054	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80749	0	0
T4	2344	1109	0	0
T5	1279	20	0	0
T6	0	762	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1110	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	352	0	0
T71	0	1142	0	0
T72	0	599	0	0
T73	0	558	0	0
T74	0	360	0	0
T75	0	19	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	476095	0	312
T1	800595	2764	0	2
T2	2228	273	0	0
T3	1833	137	0	0
T4	2344	1479	0	0
T14	2652	345	0	0
T19	1943	230	0	0
T21	0	0	0	2
T25	1054	74	0	0
T28	2508	202	0	0
T41	2630	176	0	0
T44	1440	28	0	0
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	3102	0	120
T3	1833	4	0	1
T4	2344	0	0	0
T5	1279	0	0	0
T8	0	45	0	1
T14	2652	4	0	1
T15	2100	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T27	0	3	0	1
T28	2508	0	0	0
T32	0	34	0	1
T33	0	0	0	1
T35	0	3	0	1
T36	0	3	0	1
T37	0	0	0	1
T41	2630	0	0	0
T44	1440	0	0	0
T67	0	4	0	0
T75	0	1	0	0
T78	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80749	0	0
T4	2344	1109	0	0
T5	1279	20	0	0
T6	0	762	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1110	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	352	0	0
T71	0	1142	0	0
T72	0	599	0	0
T73	0	558	0	0
T74	0	360	0	0
T75	0	19	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	476095	0	312
T1	800595	2764	0	2
T2	2228	273	0	0
T3	1833	137	0	0
T4	2344	1479	0	0
T14	2652	345	0	0
T19	1943	230	0	0
T21	0	0	0	2
T25	1054	74	0	0
T28	2508	202	0	0
T41	2630	176	0	0
T44	1440	28	0	0
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	3331	0	109
T8	2986	5	0	1
T11	1686	0	0	0
T16	8523	0	0	0
T20	2077	0	0	0
T23	0	42	0	1
T24	1065	3	0	1
T27	0	3	0	1
T33	0	0	0	1
T34	0	3	0	1
T36	0	9	0	1
T40	2232	0	0	0
T69	1391	0	0	0
T72	0	1	0	0
T78	0	3	0	1
T79	2158	0	0	0
T80	2212	0	0	0
T81	822	0	0	0
T83	0	4	0	1
T84	0	14	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80749	0	0
T4	2344	1109	0	0
T5	1279	20	0	0
T6	0	762	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1110	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	352	0	0
T71	0	1142	0	0
T72	0	599	0	0
T73	0	558	0	0
T74	0	360	0	0
T75	0	19	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	476095	0	312
T1	800595	2764	0	2
T2	2228	273	0	0
T3	1833	137	0	0
T4	2344	1479	0	0
T14	2652	345	0	0
T19	1943	230	0	0
T21	0	0	0	2
T25	1054	74	0	0
T28	2508	202	0	0
T41	2630	176	0	0
T44	1440	28	0	0
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	3283	0	101
T5	1279	0	0	0
T8	0	18	0	1
T11	1686	0	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T16	0	3	0	1
T24	1065	0	0	0
T25	1054	3	0	1
T26	0	4	0	1
T33	0	42	0	1
T35	0	41	0	1
T36	0	15	0	1
T37	0	3	0	1
T40	2232	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T69	1391	0	0	0
T85	0	3	0	1
T86	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80749	0	0
T4	2344	1109	0	0
T5	1279	20	0	0
T6	0	762	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1110	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	352	0	0
T71	0	1142	0	0
T72	0	599	0	0
T73	0	558	0	0
T74	0	360	0	0
T75	0	19	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	476095	0	312
T1	800595	2764	0	2
T2	2228	273	0	0
T3	1833	137	0	0
T4	2344	1479	0	0
T14	2652	345	0	0
T19	1943	230	0	0
T21	0	0	0	2
T25	1054	74	0	0
T28	2508	202	0	0
T41	2630	176	0	0
T44	1440	28	0	0
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	2434	0	72
T8	2986	0	0	0
T16	8523	3	0	1
T20	2077	0	0	0
T23	1210	3	0	1
T26	2051	0	0	0
T27	0	9	0	1
T33	0	3	0	1
T35	0	53	0	1
T36	0	60	0	1
T37	0	54	0	1
T39	0	3	0	1
T61	1165	0	0	0
T78	0	3	0	1
T79	2158	0	0	0
T80	2212	0	0	0
T81	822	0	0	0
T82	2054	0	0	0
T87	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80749	0	0
T4	2344	1109	0	0
T5	1279	20	0	0
T6	0	762	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1110	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	352	0	0
T71	0	1142	0	0
T72	0	599	0	0
T73	0	558	0	0
T74	0	360	0	0
T75	0	19	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	476095	0	312
T1	800595	2764	0	2
T2	2228	273	0	0
T3	1833	137	0	0
T4	2344	1479	0	0
T14	2652	345	0	0
T19	1943	230	0	0
T21	0	0	0	2
T25	1054	74	0	0
T28	2508	202	0	0
T41	2630	176	0	0
T44	1440	28	0	0
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	2622	0	80
T6	1467	0	0	0
T17	8889	0	0	0
T23	1210	14	0	1
T26	2051	4	0	0
T27	1982	3	0	1
T29	2170	0	0	0
T31	0	7	0	1
T33	0	3	0	1
T35	0	7	0	1
T36	0	41	0	1
T38	0	0	0	1
T61	1165	0	0	0
T82	2054	0	0	0
T88	0	4	0	0
T89	0	4	0	1
T90	0	3	0	1
T91	1758	0	0	0
T92	1798	0	0	0
T93	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80749	0	0
T4	2344	1109	0	0
T5	1279	20	0	0
T6	0	762	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1110	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	352	0	0
T71	0	1142	0	0
T72	0	599	0	0
T73	0	558	0	0
T74	0	360	0	0
T75	0	19	0	0