Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	245153441	10896852	0	0
boot_gen_cmd_rd_A	245153441	72239	0	0
boot_ins_cmd_rd_A	245153441	82076	0	0
ctrl_rd_A	245153441	72085	0	0
err_code_test_rd_A	245153441	81964	0	0
intr_enable_rd_A	245153441	77706	0	0
max_num_reqs_between_reseeds_rd_A	245153441	72622	0	0
regwen_rd_A	245153441	82856	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	10896852	0	0
T1	800595	269472	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T21	0	96902	0	0
T22	0	166388	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T222	0	324379	0	0
T223	0	250703	0	0
T224	0	247491	0	0
T225	0	104703	0	0
T226	0	53635	0	0
T227	0	84278	0	0
T228	0	92731	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	72239	0	0
T1	800595	7436	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T229	0	9920	0	0
T230	0	5421	0	0
T231	0	11084	0	0
T232	0	12531	0	0
T233	0	5325	0	0
T234	0	3156	0	0
T235	0	3810	0	0
T236	0	2853	0	0
T237	0	1954	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	82076	0	0
T1	800595	8517	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T229	0	11005	0	0
T230	0	6120	0	0
T231	0	12839	0	0
T232	0	14127	0	0
T233	0	5727	0	0
T234	0	3577	0	0
T235	0	4132	0	0
T236	0	3580	0	0
T237	0	2141	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	72085	0	0
T1	800595	7459	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T86	0	4	0	0
T118	0	5	0	0
T229	0	9735	0	0
T230	0	5022	0	0
T231	0	11799	0	0
T238	0	7	0	0
T239	0	3	0	0
T240	0	3	0	0
T241	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	81964	0	0
T1	800595	8684	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T229	0	10852	0	0
T230	0	6007	0	0
T231	0	12841	0	0
T232	0	14433	0	0
T233	0	5792	0	0
T234	0	3654	0	0
T235	0	4223	0	0
T236	0	3372	0	0
T237	0	2102	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	77706	0	0
T1	800595	7766	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T229	0	10357	0	0
T230	0	5104	0	0
T231	0	11723	0	0
T232	0	12586	0	0
T242	0	104	0	0
T243	0	35	0	0
T244	0	40	0	0
T245	0	19	0	0
T246	0	48	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	72622	0	0
T1	800595	7517	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T229	0	9709	0	0
T230	0	4715	0	0
T231	0	11570	0	0
T232	0	12582	0	0
T233	0	5235	0	0
T234	0	3449	0	0
T235	0	3719	0	0
T236	0	3005	0	0
T237	0	1878	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	245153441	82856	0	0
T1	800595	8827	0	0
T2	2228	0	0	0
T3	1833	0	0	0
T4	2344	0	0	0
T14	2652	0	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T229	0	11043	0	0
T230	0	6146	0	0
T231	0	12998	0	0
T232	0	13714	0	0
T233	0	5766	0	0
T234	0	3779	0	0
T235	0	4352	0	0
T236	0	3486	0	0
T237	0	2075	0	0