Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.40	98.25	93.97	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.32	99.92	92.75	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T15,T16,T9

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T17,T18
1	0	Covered	T4,T6,T13

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T37,T38	Yes	T1,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T15	Yes	T1,T3,T15	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	INPUT
edn_i[2].edn_req	Yes	Yes	T25,T19,T13	Yes	T25,T19,T13	INPUT
edn_i[3].edn_req	Yes	Yes	T4,T16,T26	Yes	T4,T16,T26	INPUT
edn_i[4].edn_req	Yes	Yes	T25,T26,T39	Yes	T25,T26,T39	INPUT
edn_i[5].edn_req	Yes	Yes	T26,T39,T13	Yes	T26,T39,T13	INPUT
edn_i[6].edn_req	Yes	Yes	T13,T40,T41	Yes	T13,T40,T41	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T25	Yes	T1,T2,T15	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T2,T3,T39	Yes	T2,T3,T39	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T25,T19,T41	Yes	T25,T19,T41	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T25,T19,T22	Yes	T25,T19,T22	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T25,T19,T41	Yes	T25,T19,T41	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T16,T26,T42	Yes	T16,T26,T42	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T26,T42,T41	Yes	T26,T42,T41	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T16,T26,T42	Yes	T16,T26,T42	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T26,T39	Yes	T25,T26,T39	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T25,T26,T40	Yes	T25,T26,T39	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T25,T26,T39	Yes	T25,T26,T39	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T39,T41,T43	Yes	T26,T39,T41	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T41,T43,T44	Yes	T41,T43,T45	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T26,T39,T41	Yes	T26,T39,T41	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T40,T41,T46	Yes	T40,T41,T47	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T41,T11,T48	Yes	T41,T46,T49	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T40,T41,T47	Yes	T40,T41,T47	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T15	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T16,T9,T50	Yes	T16,T9,T50	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T15,T16,T9	Yes	T15,T16,T9	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T51,T6	Yes	T4,T51,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T15,T16,T9	Yes	T15,T16,T9	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T51,T6	Yes	T4,T51,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T5,T52	Yes	T1,T5,T52	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T5,T52	Yes	T1,T5,T52	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	216287617	216096294	0	0
CsrngAppIfOut_A	216287617	216096294	0	0
FpvSecCmCntAlertCheck_A	216287617	116	0	0
FpvSecCmGenCmdFifoRptrCheck_A	216287617	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	216287617	80	0	0
FpvSecCmMainFsmCheck_A	216287617	80	0	0
FpvSecCmRegWeOnehotCheck_A	216287617	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	216287617	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	216287617	80	0	0
IntrEdnCmdReqDoneKnownO_A	216287617	216096294	0	0
TlAReadyKnownO_A	216287617	216096294	0	0
TlDValidKnownO_A	216287617	216096294	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	216287617	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	216287617	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	216287617	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	216287617	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	216287617	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	216287617	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	216287617	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	216287617	625020	0	326
gen_edn_if_asserts[0].EdnDataStable_A	216287617	23583	0	438
gen_edn_if_asserts[0].EdnEndPointOut_A	216287617	216096294	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	216287617	168073	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	216287617	625020	0	326
gen_edn_if_asserts[1].EdnDataStable_A	216287617	4943	0	138
gen_edn_if_asserts[1].EdnEndPointOut_A	216287617	216096294	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	216287617	168073	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	216287617	625020	0	326
gen_edn_if_asserts[2].EdnDataStable_A	216287617	4834	0	113
gen_edn_if_asserts[2].EdnEndPointOut_A	216287617	216096294	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	216287617	168073	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	216287617	625020	0	326
gen_edn_if_asserts[3].EdnDataStable_A	216287617	5421	0	106
gen_edn_if_asserts[3].EdnEndPointOut_A	216287617	216096294	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	216287617	168073	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	216287617	625020	0	326
gen_edn_if_asserts[4].EdnDataStable_A	216287617	2533	0	93
gen_edn_if_asserts[4].EdnEndPointOut_A	216287617	216096294	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	216287617	168073	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	216287617	625020	0	326
gen_edn_if_asserts[5].EdnDataStable_A	216287617	2681	0	73
gen_edn_if_asserts[5].EdnEndPointOut_A	216287617	216096294	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	216287617	168073	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	216287617	625020	0	326
gen_edn_if_asserts[6].EdnDataStable_A	216287617	2342	0	81
gen_edn_if_asserts[6].EdnEndPointOut_A	216287617	216096294	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	216287617	168073	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	116	0	0
T6	725	1	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T14	0	1	0	0
T17	0	10	0	0
T40	2859	0	0	0
T42	4173	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	80	0	0
T7	2446	0	0	0
T10	2972	0	0	0
T13	46649	20	0	0
T17	0	10	0	0
T18	0	10	0	0
T40	2859	0	0	0
T41	2113	0	0	0
T42	4173	0	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T61	1740	0	0	0
T62	1198	0	0	0
T63	0	20	0	0
T64	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	625020	0	326
T1	313199	1184	0	2
T2	3664	247	0	0
T3	1870	28	0	0
T4	1812	1035	0	0
T5	0	0	0	2
T9	2309	237	0	0
T13	0	0	0	2
T15	2676	416	0	0
T16	2379	538	0	0
T24	1934	23	0	0
T25	2850	32	0	0
T26	1537	34	0	0
T46	0	0	0	2
T51	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	23583	0	438
T1	313199	40	0	0
T2	3664	112	0	1
T3	1870	0	0	0
T4	1812	0	0	0
T5	0	25	0	0
T9	2309	4	0	1
T10	0	0	0	1
T15	2676	8	0	1
T16	2379	4	0	0
T24	1934	3	0	1
T25	2850	63	0	1
T26	1537	3	0	1
T39	0	11	0	1
T50	0	0	0	1
T59	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	168073	0	0
T4	1812	1072	0	0
T5	27360	0	0	0
T6	0	274	0	0
T7	0	1114	0	0
T9	2309	0	0	0
T13	0	18938	0	0
T14	0	420	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T30	0	25	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	290	0	0
T62	0	526	0	0
T70	0	1141	0	0
T71	0	1172	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	625020	0	326
T1	313199	1184	0	2
T2	3664	247	0	0
T3	1870	28	0	0
T4	1812	1035	0	0
T5	0	0	0	2
T9	2309	237	0	0
T13	0	0	0	2
T15	2676	416	0	0
T16	2379	538	0	0
T24	1934	23	0	0
T25	2850	32	0	0
T26	1537	34	0	0
T46	0	0	0	2
T51	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	4943	0	138
T2	3664	59	0	1
T3	1870	15	0	1
T4	1812	0	0	0
T9	2309	0	0	0
T15	2676	0	0	0
T16	2379	0	0	0
T19	0	4	0	1
T21	0	399	0	1
T24	1934	0	0	0
T25	2850	3	0	1
T26	1537	3	0	1
T39	0	52	0	1
T42	0	11	0	1
T45	0	3	0	1
T51	1440	0	0	0
T72	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	168073	0	0
T4	1812	1072	0	0
T5	27360	0	0	0
T6	0	274	0	0
T7	0	1114	0	0
T9	2309	0	0	0
T13	0	18938	0	0
T14	0	420	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T30	0	25	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	290	0	0
T62	0	526	0	0
T70	0	1141	0	0
T71	0	1172	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	625020	0	326
T1	313199	1184	0	2
T2	3664	247	0	0
T3	1870	28	0	0
T4	1812	1035	0	0
T5	0	0	0	2
T9	2309	237	0	0
T13	0	0	0	2
T15	2676	416	0	0
T16	2379	538	0	0
T24	1934	23	0	0
T25	2850	32	0	0
T26	1537	34	0	0
T46	0	0	0	2
T51	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	4834	0	113
T5	27360	0	0	0
T9	2309	0	0	0
T12	0	0	0	1
T16	2379	0	0	0
T19	2069	4	0	0
T22	0	435	0	1
T25	2850	33	0	1
T26	1537	0	0	0
T39	3374	0	0	0
T41	0	3	0	1
T44	0	3	0	1
T50	2789	0	0	0
T51	1440	0	0	0
T52	16725	0	0	0
T73	0	987	0	1
T74	0	4	0	0
T75	0	3	0	1
T76	0	21	0	1
T77	0	8	0	1
T78	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	168073	0	0
T4	1812	1072	0	0
T5	27360	0	0	0
T6	0	274	0	0
T7	0	1114	0	0
T9	2309	0	0	0
T13	0	18938	0	0
T14	0	420	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T30	0	25	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	290	0	0
T62	0	526	0	0
T70	0	1141	0	0
T71	0	1172	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	625020	0	326
T1	313199	1184	0	2
T2	3664	247	0	0
T3	1870	28	0	0
T4	1812	1035	0	0
T5	0	0	0	2
T9	2309	237	0	0
T13	0	0	0	2
T15	2676	416	0	0
T16	2379	538	0	0
T24	1934	23	0	0
T25	2850	32	0	0
T26	1537	34	0	0
T46	0	0	0	2
T51	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	5421	0	106
T5	27360	0	0	0
T6	725	0	0	0
T9	2309	0	0	0
T12	0	0	0	1
T16	2379	4	0	1
T19	2069	0	0	0
T26	1537	23	0	1
T39	3374	0	0	0
T41	0	17	0	1
T42	0	12	0	1
T50	2789	0	0	0
T51	1440	0	0	0
T52	16725	0	0	0
T75	0	69	0	1
T76	0	3	0	1
T79	0	3	0	1
T80	0	4	0	0
T81	0	3	0	1
T82	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	168073	0	0
T4	1812	1072	0	0
T5	27360	0	0	0
T6	0	274	0	0
T7	0	1114	0	0
T9	2309	0	0	0
T13	0	18938	0	0
T14	0	420	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T30	0	25	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	290	0	0
T62	0	526	0	0
T70	0	1141	0	0
T71	0	1172	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	625020	0	326
T1	313199	1184	0	2
T2	3664	247	0	0
T3	1870	28	0	0
T4	1812	1035	0	0
T5	0	0	0	2
T9	2309	237	0	0
T13	0	0	0	2
T15	2676	416	0	0
T16	2379	538	0	0
T24	1934	23	0	0
T25	2850	32	0	0
T26	1537	34	0	0
T46	0	0	0	2
T51	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	2533	0	93
T5	27360	0	0	0
T9	2309	0	0	0
T16	2379	0	0	0
T19	2069	0	0	0
T22	0	3	0	1
T25	2850	63	0	1
T26	1537	44	0	1
T39	3374	3	0	1
T40	0	4	0	0
T41	0	3	0	1
T45	0	58	0	1
T50	2789	0	0	0
T51	1440	0	0	0
T52	16725	0	0	0
T54	0	1	0	0
T75	0	61	0	1
T76	0	3	0	1
T83	0	0	0	1
T84	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	168073	0	0
T4	1812	1072	0	0
T5	27360	0	0	0
T6	0	274	0	0
T7	0	1114	0	0
T9	2309	0	0	0
T13	0	18938	0	0
T14	0	420	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T30	0	25	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	290	0	0
T62	0	526	0	0
T70	0	1141	0	0
T71	0	1172	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	625020	0	326
T1	313199	1184	0	2
T2	3664	247	0	0
T3	1870	28	0	0
T4	1812	1035	0	0
T5	0	0	0	2
T9	2309	237	0	0
T13	0	0	0	2
T15	2676	416	0	0
T16	2379	538	0	0
T24	1934	23	0	0
T25	2850	32	0	0
T26	1537	34	0	0
T46	0	0	0	2
T51	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	2681	0	73
T5	27360	0	0	0
T6	725	0	0	0
T10	2972	0	0	0
T13	46649	0	0	0
T19	2069	0	0	0
T26	1537	3	0	1
T39	3374	3	0	1
T41	0	58	0	1
T43	0	4	0	0
T44	0	68	0	1
T45	0	12	0	1
T50	2789	0	0	0
T51	1440	0	0	0
T52	16725	0	0	0
T85	0	49	0	1
T86	0	3	0	1
T87	0	3	0	1
T88	0	4	0	0
T89	0	0	0	1
T90	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	168073	0	0
T4	1812	1072	0	0
T5	27360	0	0	0
T6	0	274	0	0
T7	0	1114	0	0
T9	2309	0	0	0
T13	0	18938	0	0
T14	0	420	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T30	0	25	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	290	0	0
T62	0	526	0	0
T70	0	1141	0	0
T71	0	1172	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	625020	0	326
T1	313199	1184	0	2
T2	3664	247	0	0
T3	1870	28	0	0
T4	1812	1035	0	0
T5	0	0	0	2
T9	2309	237	0	0
T13	0	0	0	2
T15	2676	416	0	0
T16	2379	538	0	0
T24	1934	23	0	0
T25	2850	32	0	0
T26	1537	34	0	0
T46	0	0	0	2
T51	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	2342	0	81
T11	0	48	0	1
T14	1849	0	0	0
T20	1189	0	0	0
T23	2611	0	0	0
T40	2859	4	0	1
T41	2113	47	0	1
T46	0	4	0	0
T47	0	3	0	1
T48	0	42	0	1
T49	0	4	0	1
T62	1198	0	0	0
T70	2195	0	0	0
T87	0	0	0	1
T91	0	3	0	1
T92	0	4	0	0
T93	0	4	0	1
T94	1197	0	0	0
T95	1625	0	0	0
T96	33388	0	0	0
T97	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	168073	0	0
T4	1812	1072	0	0
T5	27360	0	0	0
T6	0	274	0	0
T7	0	1114	0	0
T9	2309	0	0	0
T13	0	18938	0	0
T14	0	420	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T30	0	25	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	290	0	0
T62	0	526	0	0
T70	0	1141	0	0
T71	0	1172	0	0