Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	216809593	9701310	0	0
boot_gen_cmd_rd_A	216809593	56341	0	0
boot_ins_cmd_rd_A	216809593	64621	0	0
ctrl_rd_A	216809593	56845	0	0
err_code_test_rd_A	216809593	64265	0	0
intr_enable_rd_A	216809593	63510	0	0
max_num_reqs_between_reseeds_rd_A	216809593	58404	0	0
regwen_rd_A	216809593	67605	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	9701310	0	0
T1	313199	176778	0	0
T2	3664	0	0	0
T3	1870	0	0	0
T4	1812	0	0	0
T9	2309	0	0	0
T15	2676	0	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T37	0	179842	0	0
T38	0	303578	0	0
T207	0	16583	0	0
T230	0	397203	0	0
T231	0	120804	0	0
T232	0	105911	0	0
T233	0	285698	0	0
T234	0	238999	0	0
T235	0	263868	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	56341	0	0
T37	534615	5226	0	0
T75	4335	0	0	0
T76	3889	0	0	0
T81	1011	0	0	0
T119	1933	0	0	0
T231	0	3579	0	0
T236	0	1737	0	0
T237	0	1350	0	0
T238	0	4765	0	0
T239	0	335	0	0
T240	0	12411	0	0
T241	0	2058	0	0
T242	0	2607	0	0
T243	0	3420	0	0
T244	919	0	0	0
T245	1162	0	0	0
T246	1904	0	0	0
T247	975	0	0	0
T248	7349	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	64621	0	0
T37	534615	6005	0	0
T75	4335	0	0	0
T76	3889	0	0	0
T81	1011	0	0	0
T119	1933	0	0	0
T231	0	4248	0	0
T236	0	1806	0	0
T237	0	1608	0	0
T238	0	5649	0	0
T239	0	507	0	0
T240	0	14116	0	0
T241	0	2294	0	0
T242	0	2954	0	0
T243	0	4194	0	0
T244	919	0	0	0
T245	1162	0	0	0
T246	1904	0	0	0
T247	975	0	0	0
T248	7349	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	56845	0	0
T5	27360	5	0	0
T6	725	0	0	0
T10	2972	0	0	0
T13	46649	0	0	0
T19	2069	0	0	0
T37	0	5180	0	0
T42	4173	0	0	0
T50	2789	0	0	0
T52	16725	8	0	0
T59	2404	0	0	0
T60	28175	0	0	0
T62	0	1	0	0
T77	0	5	0	0
T126	0	6	0	0
T231	0	3549	0	0
T236	0	1673	0	0
T248	0	2	0	0
T249	0	8	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	64265	0	0
T37	534615	6043	0	0
T75	4335	0	0	0
T76	3889	0	0	0
T81	1011	0	0	0
T119	1933	0	0	0
T231	0	4020	0	0
T236	0	1974	0	0
T237	0	1422	0	0
T238	0	5675	0	0
T239	0	568	0	0
T240	0	14161	0	0
T241	0	2209	0	0
T242	0	3197	0	0
T243	0	4036	0	0
T244	919	0	0	0
T245	1162	0	0	0
T246	1904	0	0	0
T247	975	0	0	0
T248	7349	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	63510	0	0
T5	27360	152	0	0
T6	725	0	0	0
T10	2972	0	0	0
T13	46649	0	0	0
T19	2069	0	0	0
T37	0	5634	0	0
T42	4173	0	0	0
T50	2789	0	0	0
T52	16725	56	0	0
T59	2404	0	0	0
T60	28175	39	0	0
T111	0	22	0	0
T231	0	3925	0	0
T236	0	1954	0	0
T237	0	1523	0	0
T249	0	69	0	0
T250	0	6	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	58404	0	0
T37	534615	5408	0	0
T75	4335	0	0	0
T76	3889	0	0	0
T81	1011	0	0	0
T119	1933	0	0	0
T231	0	3365	0	0
T236	0	1604	0	0
T237	0	1396	0	0
T238	0	4829	0	0
T239	0	432	0	0
T240	0	12642	0	0
T241	0	1883	0	0
T242	0	2595	0	0
T243	0	3775	0	0
T244	919	0	0	0
T245	1162	0	0	0
T246	1904	0	0	0
T247	975	0	0	0
T248	7349	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216809593	67605	0	0
T37	534615	6051	0	0
T75	4335	0	0	0
T76	3889	0	0	0
T81	1011	0	0	0
T119	1933	0	0	0
T231	0	4047	0	0
T236	0	2017	0	0
T237	0	1527	0	0
T238	0	5818	0	0
T239	0	442	0	0
T240	0	14454	0	0
T241	0	2454	0	0
T242	0	2929	0	0
T243	0	4189	0	0
T244	919	0	0	0
T245	1162	0	0	0
T246	1904	0	0	0
T247	975	0	0	0
T248	7349	0	0	0