Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.25	93.91	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.02	99.92	92.66	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T18,T19,T9

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Covered	T4,T5,T39

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T18,T19	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T19,T28	Yes	T1,T19,T28	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T18	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T18	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T18	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T18	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T29,T4,T9	Yes	T29,T4,T9	INPUT
edn_i[2].edn_req	Yes	Yes	T27,T19,T33	Yes	T27,T19,T33	INPUT
edn_i[3].edn_req	Yes	Yes	T27,T39,T23	Yes	T27,T39,T23	INPUT
edn_i[4].edn_req	Yes	Yes	T23,T46,T47	Yes	T23,T46,T47	INPUT
edn_i[5].edn_req	Yes	Yes	T46,T47,T25	Yes	T46,T47,T25	INPUT
edn_i[6].edn_req	Yes	Yes	T18,T33,T48	Yes	T18,T33,T48	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T28	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T29,T9,T10	Yes	T29,T9,T33	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T46,T49,T25	Yes	T29,T9,T33	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T29,T4,T9	Yes	T29,T4,T9	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T33,T11,T46	Yes	T19,T33,T11	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T46,T49,T50	Yes	T19,T33,T11	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T27,T19,T33	Yes	T27,T19,T33	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T23,T46,T47	Yes	T27,T23,T46	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T23,T49,T51	Yes	T23,T46,T49	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T27,T23,T46	Yes	T27,T23,T46	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T46,T47,T49	Yes	T46,T47,T49	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T47,T49,T25	Yes	T23,T47,T49	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T23,T46,T47	Yes	T23,T46,T47	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T46,T47,T25	Yes	T46,T47,T25	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T47,T52,T53	Yes	T46,T47,T54	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T46,T47,T25	Yes	T46,T47,T25	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T18,T33,T48	Yes	T18,T33,T48	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T33,T46,T50	Yes	T18,T33,T46	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T18,T33,T48	Yes	T18,T33,T48	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T33	Yes	T1,T2,T19	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T28	Yes	T1,T2,T18	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T11,T55,T56	Yes	T11,T55,T56	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T19,T9	Yes	T18,T19,T9	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T39	Yes	T4,T5,T39	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T19,T9	Yes	T18,T19,T9	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T39	Yes	T4,T5,T39	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T2,T43,T57	Yes	T2,T43,T57	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T4,T43	Yes	T2,T4,T43	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	195149815	194993143	0	0
CsrngAppIfOut_A	195149815	194993143	0	0
FpvSecCmCntAlertCheck_A	195149815	92	0	0
FpvSecCmGenCmdFifoRptrCheck_A	195149815	50	0	0
FpvSecCmGenCmdFifoWptrCheck_A	195149815	50	0	0
FpvSecCmMainFsmCheck_A	195149815	50	0	0
FpvSecCmRegWeOnehotCheck_A	195149815	50	0	0
FpvSecCmResCmdFifoRptrCheck_A	195149815	50	0	0
FpvSecCmResCmdFifoWptrCheck_A	195149815	50	0	0
IntrEdnCmdReqDoneKnownO_A	195149815	194993143	0	0
TlAReadyKnownO_A	195149815	194993143	0	0
TlDValidKnownO_A	195149815	194993143	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	195149815	50	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	195149815	50	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	195149815	50	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	195149815	50	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	195149815	50	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	195149815	50	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	195149815	50	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	195149815	555733	0	326
gen_edn_if_asserts[0].EdnDataStable_A	195149815	22505	0	407
gen_edn_if_asserts[0].EdnEndPointOut_A	195149815	194993143	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	195149815	136128	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	195149815	555733	0	326
gen_edn_if_asserts[1].EdnDataStable_A	195149815	5398	0	143
gen_edn_if_asserts[1].EdnEndPointOut_A	195149815	194993143	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	195149815	136128	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	195149815	555733	0	326
gen_edn_if_asserts[2].EdnDataStable_A	195149815	4556	0	129
gen_edn_if_asserts[2].EdnEndPointOut_A	195149815	194993143	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	195149815	136128	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	195149815	555733	0	326
gen_edn_if_asserts[3].EdnDataStable_A	195149815	53461	0	106
gen_edn_if_asserts[3].EdnEndPointOut_A	195149815	194993143	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	195149815	136128	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	195149815	555733	0	326
gen_edn_if_asserts[4].EdnDataStable_A	195149815	3140	0	113
gen_edn_if_asserts[4].EdnEndPointOut_A	195149815	194993143	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	195149815	136128	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	195149815	555733	0	326
gen_edn_if_asserts[5].EdnDataStable_A	195149815	4980	0	92
gen_edn_if_asserts[5].EdnEndPointOut_A	195149815	194993143	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	195149815	136128	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	195149815	555733	0	326
gen_edn_if_asserts[6].EdnDataStable_A	195149815	5316	0	93
gen_edn_if_asserts[6].EdnEndPointOut_A	195149815	194993143	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	195149815	136128	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	92	0	0
T7	1175	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	1159	0	0	0
T66	2565	0	0	0
T67	2114	0	0	0
T68	1641	0	0	0
T69	2133	0	0	0
T70	1879	0	0	0
T71	2829	0	0	0
T72	2530	0	0	0
T73	1362	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	50	0	0
T20	27155	10	0	0
T21	0	10	0	0
T22	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T76	1914	0	0	0
T77	4427	0	0	0
T78	210448	0	0	0
T79	708	0	0	0
T80	2974	0	0	0
T81	3053	0	0	0
T82	3197	0	0	0
T83	2266	0	0	0
T84	2131	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	555733	0	326
T1	2647	47	0	0
T2	32263	2974	0	2
T3	891	73	0	0
T4	895	279	0	0
T9	2314	306	0	0
T10	0	0	0	2
T18	2590	459	0	0
T19	2364	361	0	0
T27	3281	33	0	0
T28	2459	17	0	0
T29	3953	12	0	0
T43	0	0	0	2
T57	0	0	0	2
T69	0	0	0	2
T85	0	0	0	2
T86	0	0	0	2
T87	0	0	0	2
T88	0	0	0	2
T89	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	22505	0	407
T1	2647	37	0	1
T2	32263	45	0	0
T3	891	3	0	1
T4	895	0	0	0
T9	2314	0	0	0
T11	0	4	0	0
T15	0	538	0	1
T18	2590	0	0	0
T19	2364	0	0	0
T27	3281	0	0	0
T28	2459	5	0	1
T29	3953	0	0	0
T33	0	21	0	1
T46	0	55	0	1
T47	0	0	0	1
T49	0	0	0	1
T90	0	3	0	1
T91	0	33	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	136128	0	0
T4	895	360	0	0
T5	1146	628	0	0
T6	0	303	0	0
T7	0	348	0	0
T8	0	386	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T34	0	19	0	0
T37	0	27	0	0
T39	1097	592	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1112	0	0
T93	0	592	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	555733	0	326
T1	2647	47	0	0
T2	32263	2974	0	2
T3	891	73	0	0
T4	895	279	0	0
T9	2314	306	0	0
T10	0	0	0	2
T18	2590	459	0	0
T19	2364	361	0	0
T27	3281	33	0	0
T28	2459	17	0	0
T29	3953	12	0	0
T43	0	0	0	2
T57	0	0	0	2
T69	0	0	0	2
T85	0	0	0	2
T86	0	0	0	2
T87	0	0	0	2
T88	0	0	0	2
T89	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	5398	0	143
T4	895	1	0	0
T5	1146	0	0	0
T9	2314	4	0	1
T10	3387	4	0	0
T25	0	1196	0	1
T29	3953	3	0	1
T33	3693	3	0	1
T39	1097	0	0	0
T46	0	14	0	1
T49	0	43	0	1
T50	0	26	0	1
T51	0	0	0	1
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	0	0	0
T94	0	24	0	1
T95	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	136128	0	0
T4	895	360	0	0
T5	1146	628	0	0
T6	0	303	0	0
T7	0	348	0	0
T8	0	386	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T34	0	19	0	0
T37	0	27	0	0
T39	1097	592	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1112	0	0
T93	0	592	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	555733	0	326
T1	2647	47	0	0
T2	32263	2974	0	2
T3	891	73	0	0
T4	895	279	0	0
T9	2314	306	0	0
T10	0	0	0	2
T18	2590	459	0	0
T19	2364	361	0	0
T27	3281	33	0	0
T28	2459	17	0	0
T29	3953	12	0	0
T43	0	0	0	2
T57	0	0	0	2
T69	0	0	0	2
T85	0	0	0	2
T86	0	0	0	2
T87	0	0	0	2
T88	0	0	0	2
T89	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	4556	0	129
T4	895	0	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	0	4	0	1
T19	2364	4	0	1
T25	0	3	0	1
T26	0	3	0	1
T27	3281	3	0	1
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	6	0	1
T46	0	23	0	1
T47	0	3	0	1
T49	0	23	0	1
T50	0	23	0	1
T90	3536	0	0	0
T91	5620	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	136128	0	0
T4	895	360	0	0
T5	1146	628	0	0
T6	0	303	0	0
T7	0	348	0	0
T8	0	386	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T34	0	19	0	0
T37	0	27	0	0
T39	1097	592	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1112	0	0
T93	0	592	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	555733	0	326
T1	2647	47	0	0
T2	32263	2974	0	2
T3	891	73	0	0
T4	895	279	0	0
T9	2314	306	0	0
T10	0	0	0	2
T18	2590	459	0	0
T19	2364	361	0	0
T27	3281	33	0	0
T28	2459	17	0	0
T29	3953	12	0	0
T43	0	0	0	2
T57	0	0	0	2
T69	0	0	0	2
T85	0	0	0	2
T86	0	0	0	2
T87	0	0	0	2
T88	0	0	0	2
T89	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	53461	0	106
T4	895	0	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T19	2364	0	0	0
T23	0	615	0	1
T27	3281	3	0	1
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	0	0	0
T46	0	16	0	1
T47	0	3	0	1
T49	0	53	0	1
T51	0	30	0	1
T69	0	4	0	0
T71	0	53	0	1
T90	3536	0	0	0
T91	5620	0	0	0
T96	0	4	0	0
T97	0	63	0	1
T98	0	0	0	1
T99	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	136128	0	0
T4	895	360	0	0
T5	1146	628	0	0
T6	0	303	0	0
T7	0	348	0	0
T8	0	386	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T34	0	19	0	0
T37	0	27	0	0
T39	1097	592	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1112	0	0
T93	0	592	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	555733	0	326
T1	2647	47	0	0
T2	32263	2974	0	2
T3	891	73	0	0
T4	895	279	0	0
T9	2314	306	0	0
T10	0	0	0	2
T18	2590	459	0	0
T19	2364	361	0	0
T27	3281	33	0	0
T28	2459	17	0	0
T29	3953	12	0	0
T43	0	0	0	2
T57	0	0	0	2
T69	0	0	0	2
T85	0	0	0	2
T86	0	0	0	2
T87	0	0	0	2
T88	0	0	0	2
T89	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	3140	0	113
T6	1277	0	0	0
T23	5897	3	0	1
T25	8637	38	0	1
T46	2645	3	0	1
T47	2607	37	0	1
T49	3893	39	0	1
T51	0	3	0	1
T54	1526	0	0	0
T55	0	4	0	1
T85	890	0	0	0
T99	0	49	0	1
T100	0	8	0	1
T101	0	4	0	1
T102	937	0	0	0
T103	1190	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	136128	0	0
T4	895	360	0	0
T5	1146	628	0	0
T6	0	303	0	0
T7	0	348	0	0
T8	0	386	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T34	0	19	0	0
T37	0	27	0	0
T39	1097	592	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1112	0	0
T93	0	592	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	555733	0	326
T1	2647	47	0	0
T2	32263	2974	0	2
T3	891	73	0	0
T4	895	279	0	0
T9	2314	306	0	0
T10	0	0	0	2
T18	2590	459	0	0
T19	2364	361	0	0
T27	3281	33	0	0
T28	2459	17	0	0
T29	3953	12	0	0
T43	0	0	0	2
T57	0	0	0	2
T69	0	0	0	2
T85	0	0	0	2
T86	0	0	0	2
T87	0	0	0	2
T88	0	0	0	2
T89	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	4980	0	92
T6	1277	0	0	0
T25	8637	3	0	1
T43	885874	0	0	0
T46	2645	3	0	1
T47	2607	24	0	1
T49	3893	0	0	0
T52	0	0	0	1
T54	1526	3	0	1
T56	0	4	0	1
T66	0	4	0	1
T85	890	0	0	0
T86	0	1	0	0
T94	0	3	0	1
T102	937	0	0	0
T103	1190	0	0	0
T104	0	4	0	1
T105	0	4	0	0
T106	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	136128	0	0
T4	895	360	0	0
T5	1146	628	0	0
T6	0	303	0	0
T7	0	348	0	0
T8	0	386	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T34	0	19	0	0
T37	0	27	0	0
T39	1097	592	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1112	0	0
T93	0	592	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	555733	0	326
T1	2647	47	0	0
T2	32263	2974	0	2
T3	891	73	0	0
T4	895	279	0	0
T9	2314	306	0	0
T10	0	0	0	2
T18	2590	459	0	0
T19	2364	361	0	0
T27	3281	33	0	0
T28	2459	17	0	0
T29	3953	12	0	0
T43	0	0	0	2
T57	0	0	0	2
T69	0	0	0	2
T85	0	0	0	2
T86	0	0	0	2
T87	0	0	0	2
T88	0	0	0	2
T89	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	5316	0	93
T4	895	0	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T18	2590	8	0	1
T19	2364	0	0	0
T27	3281	0	0	0
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	19	0	1
T46	0	35	0	1
T47	0	3	0	1
T48	0	3	0	1
T50	0	56	0	1
T51	0	3	0	1
T86	0	4	0	0
T88	0	4	0	0
T90	3536	0	0	0
T94	0	3	0	1
T107	0	0	0	1
T108	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	136128	0	0
T4	895	360	0	0
T5	1146	628	0	0
T6	0	303	0	0
T7	0	348	0	0
T8	0	386	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T34	0	19	0	0
T37	0	27	0	0
T39	1097	592	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1112	0	0
T93	0	592	0	0