Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	195624060	8376257	0	0
boot_gen_cmd_rd_A	195624060	74867	0	0
boot_ins_cmd_rd_A	195624060	85943	0	0
ctrl_rd_A	195624060	76111	0	0
err_code_test_rd_A	195624060	86964	0	0
intr_enable_rd_A	195624060	82807	0	0
max_num_reqs_between_reseeds_rd_A	195624060	76602	0	0
regwen_rd_A	195624060	86818	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	8376257	0	0
T24	2454	0	0	0
T26	1339	0	0	0
T30	905	0	0	0
T43	885874	321160	0	0
T44	0	90942	0	0
T45	0	429581	0	0
T50	3194	0	0	0
T55	2573	0	0	0
T56	2132	0	0	0
T57	14202	0	0	0
T86	1601	0	0	0
T87	11680	0	0	0
T116	0	59829	0	0
T123	0	299614	0	0
T124	0	229560	0	0
T125	0	240779	0	0
T238	0	29343	0	0
T239	0	106865	0	0
T240	0	35085	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	74867	0	0
T24	2454	0	0	0
T26	1339	0	0	0
T30	905	0	0	0
T43	885874	4882	0	0
T50	3194	0	0	0
T55	2573	0	0	0
T56	2132	0	0	0
T57	14202	0	0	0
T78	0	2119	0	0
T86	1601	0	0	0
T87	11680	0	0	0
T240	0	995	0	0
T241	0	5343	0	0
T242	0	9556	0	0
T243	0	5056	0	0
T244	0	1671	0	0
T245	0	1792	0	0
T246	0	5743	0	0
T247	0	2700	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	85943	0	0
T24	2454	0	0	0
T26	1339	0	0	0
T30	905	0	0	0
T43	885874	5054	0	0
T50	3194	0	0	0
T55	2573	0	0	0
T56	2132	0	0	0
T57	14202	0	0	0
T78	0	2323	0	0
T86	1601	0	0	0
T87	11680	0	0	0
T240	0	1167	0	0
T241	0	5808	0	0
T242	0	11319	0	0
T243	0	5752	0	0
T244	0	2196	0	0
T245	0	1960	0	0
T246	0	6779	0	0
T247	0	3241	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	76111	0	0
T2	32263	7	0	0
T3	891	0	0	0
T4	895	0	0	0
T9	2314	0	0	0
T18	2590	0	0	0
T19	2364	0	0	0
T27	3281	0	0	0
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	0	0	0
T43	0	5142	0	0
T69	0	1	0	0
T101	0	4	0	0
T240	0	981	0	0
T241	0	5289	0	0
T242	0	10018	0	0
T248	0	4	0	0
T249	0	7	0	0
T250	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	86964	0	0
T24	2454	0	0	0
T26	1339	0	0	0
T30	905	0	0	0
T43	885874	5570	0	0
T50	3194	0	0	0
T55	2573	0	0	0
T56	2132	0	0	0
T57	14202	0	0	0
T78	0	2311	0	0
T86	1601	0	0	0
T87	11680	0	0	0
T240	0	1179	0	0
T241	0	5625	0	0
T242	0	11243	0	0
T243	0	5906	0	0
T244	0	2154	0	0
T245	0	2068	0	0
T246	0	7136	0	0
T247	0	3355	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	82807	0	0
T2	32263	44	0	0
T3	891	0	0	0
T4	895	0	0	0
T9	2314	0	0	0
T18	2590	0	0	0
T19	2364	0	0	0
T27	3281	0	0	0
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	0	0	0
T43	0	4897	0	0
T78	0	2459	0	0
T87	0	39	0	0
T240	0	1203	0	0
T241	0	5129	0	0
T242	0	10337	0	0
T243	0	5442	0	0
T250	0	38	0	0
T251	0	51	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	76602	0	0
T24	2454	0	0	0
T26	1339	0	0	0
T30	905	0	0	0
T43	885874	4791	0	0
T50	3194	0	0	0
T55	2573	0	0	0
T56	2132	0	0	0
T57	14202	0	0	0
T78	0	2161	0	0
T86	1601	0	0	0
T87	11680	0	0	0
T240	0	1101	0	0
T241	0	5052	0	0
T242	0	9941	0	0
T243	0	4993	0	0
T244	0	1783	0	0
T245	0	1693	0	0
T246	0	6022	0	0
T247	0	2687	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195624060	86818	0	0
T24	2454	0	0	0
T26	1339	0	0	0
T30	905	0	0	0
T43	885874	5682	0	0
T50	3194	0	0	0
T55	2573	0	0	0
T56	2132	0	0	0
T57	14202	0	0	0
T78	0	2538	0	0
T86	1601	0	0	0
T87	11680	0	0	0
T240	0	1135	0	0
T241	0	5822	0	0
T242	0	11081	0	0
T243	0	5833	0	0
T244	0	2061	0	0
T245	0	1878	0	0
T246	0	6733	0	0
T247	0	3267	0	0