Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.25	93.91	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.02	99.92	92.66	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T18,T19
1	0	Covered	T4,T5,T26

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T10	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T5	Yes	T2,T10,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T6,T36,T37	Yes	T6,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T24,T10	Yes	T3,T24,T10	INPUT
edn_i[1].edn_req	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T38,T41	Yes	T4,T38,T41	INPUT
edn_i[3].edn_req	Yes	Yes	T41,T16,T42	Yes	T41,T16,T42	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T24	Yes	T1,T2,T24	INPUT
edn_i[5].edn_req	Yes	Yes	T24,T16,T43	Yes	T24,T16,T43	INPUT
edn_i[6].edn_req	Yes	Yes	T5,T41,T16	Yes	T5,T41,T16	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T10,T6	Yes	T3,T10,T6	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T10,T6,T44	Yes	T24,T10,T6	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T24,T10	Yes	T3,T24,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T38,T39,T45	Yes	T38,T39,T46	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T8,T47,T48	Yes	T38,T39,T40	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T38,T41,T15	Yes	T38,T41,T15	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T38,T42,T49	Yes	T38,T41,T15	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T38,T41,T15	Yes	T38,T41,T15	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T41,T42,T47	Yes	T41,T42,T47	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T47,T50,T51	Yes	T42,T47,T21	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T41,T42,T47	Yes	T41,T42,T47	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T2,T24	Yes	T1,T2,T24	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T21,T50,T22	Yes	T1,T41,T21	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T2,T24	Yes	T1,T2,T24	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T24,T43,T42	Yes	T24,T43,T42	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T24,T52,T53	Yes	T24,T43,T42	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T24,T43,T42	Yes	T24,T43,T42	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T5,T41,T42	Yes	T5,T41,T43	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T5,T41,T48	Yes	T5,T41,T54	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T5,T41,T43	Yes	T5,T41,T43	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T24,T10	Yes	T1,T24,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T24,T10,T6	Yes	T1,T24,T6	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T38,T55,T56	Yes	T38,T55,T56	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T36,T57	Yes	T6,T36,T57	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T6,T26	Yes	T5,T6,T26	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	234015551	233838813	0	0
CsrngAppIfOut_A	234015551	233838813	0	0
FpvSecCmCntAlertCheck_A	234015551	110	0	0
FpvSecCmGenCmdFifoRptrCheck_A	234015551	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	234015551	70	0	0
FpvSecCmMainFsmCheck_A	234015551	70	0	0
FpvSecCmRegWeOnehotCheck_A	234015551	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	234015551	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	234015551	70	0	0
IntrEdnCmdReqDoneKnownO_A	234015551	233838813	0	0
TlAReadyKnownO_A	234015551	233838813	0	0
TlDValidKnownO_A	234015551	233838813	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	234015551	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	234015551	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	234015551	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	234015551	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	234015551	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	234015551	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	234015551	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	234015551	580574	0	312
gen_edn_if_asserts[0].EdnDataStable_A	234015551	25413	0	431
gen_edn_if_asserts[0].EdnEndPointOut_A	234015551	233838813	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	234015551	149504	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	234015551	580574	0	312
gen_edn_if_asserts[1].EdnDataStable_A	234015551	2624	0	146
gen_edn_if_asserts[1].EdnEndPointOut_A	234015551	233838813	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	234015551	149504	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	234015551	580574	0	312
gen_edn_if_asserts[2].EdnDataStable_A	234015551	2916	0	124
gen_edn_if_asserts[2].EdnEndPointOut_A	234015551	233838813	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	234015551	149504	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	234015551	580574	0	312
gen_edn_if_asserts[3].EdnDataStable_A	234015551	4234	0	117
gen_edn_if_asserts[3].EdnEndPointOut_A	234015551	233838813	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	234015551	149504	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	234015551	580574	0	312
gen_edn_if_asserts[4].EdnDataStable_A	234015551	3751	0	115
gen_edn_if_asserts[4].EdnEndPointOut_A	234015551	233838813	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	234015551	149504	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	234015551	580574	0	312
gen_edn_if_asserts[5].EdnDataStable_A	234015551	4598	0	91
gen_edn_if_asserts[5].EdnEndPointOut_A	234015551	233838813	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	234015551	149504	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	234015551	580574	0	312
gen_edn_if_asserts[6].EdnDataStable_A	234015551	2152	0	85
gen_edn_if_asserts[6].EdnEndPointOut_A	234015551	233838813	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	234015551	149504	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	110	0	0
T4	1597	1	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T10	2699	0	0	0
T16	0	10	0	0
T17	0	1	0	0
T18	0	20	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	1959	0	0	0
T65	937	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	70	0	0
T16	23364	10	0	0
T17	1118	0	0	0
T18	0	20	0	0
T19	0	10	0	0
T20	3011	0	0	0
T36	800647	0	0	0
T42	2148	0	0	0
T43	2917	0	0	0
T45	2009	0	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	1455	0	0	0
T69	3332	0	0	0
T70	1353	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	580574	0	312
T1	1819	130	0	0
T2	1786	195	0	0
T3	1790	127	0	0
T4	1597	912	0	0
T5	1089	526	0	0
T6	994866	1502	0	2
T10	2699	266	0	0
T15	0	0	0	2
T16	0	0	0	2
T24	1318	26	0	0
T25	1363	11	0	0
T26	1898	988	0	0
T36	0	0	0	2
T37	0	0	0	2
T54	0	0	0	2
T64	0	0	0	2
T69	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	25413	0	431
T3	1790	8	0	1
T4	1597	0	0	0
T5	1089	0	0	0
T6	994866	148	0	0
T10	2699	15	0	1
T24	1318	3	0	1
T25	1363	3	0	1
T26	1898	0	0	0
T31	0	1	0	0
T38	2273	0	0	0
T39	0	0	0	1
T44	0	78	0	1
T64	1959	0	0	0
T65	0	3	0	1
T73	0	37	0	1
T74	0	15	0	1
T75	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	149504	0	0
T4	1597	923	0	0
T5	1089	7	0	0
T6	994866	0	0	0
T7	0	352	0	0
T8	0	1032	0	0
T10	2699	0	0	0
T16	0	9433	0	0
T17	0	624	0	0
T25	1363	0	0	0
T26	1898	7	0	0
T31	0	7	0	0
T32	0	1070	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	354	0	0
T64	1959	0	0	0
T65	937	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	580574	0	312
T1	1819	130	0	0
T2	1786	195	0	0
T3	1790	127	0	0
T4	1597	912	0	0
T5	1089	526	0	0
T6	994866	1502	0	2
T10	2699	266	0	0
T15	0	0	0	2
T16	0	0	0	2
T24	1318	26	0	0
T25	1363	11	0	0
T26	1898	988	0	0
T36	0	0	0	2
T37	0	0	0	2
T54	0	0	0	2
T64	0	0	0	2
T69	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	2624	0	146
T7	786	0	0	0
T8	0	1	0	0
T31	1898	0	0	0
T38	2273	4	0	1
T39	1899	14	0	1
T40	0	3	0	1
T41	3438	0	0	0
T42	0	3	0	1
T44	3356	0	0	0
T45	0	8	0	1
T46	0	3	0	1
T47	0	19	0	1
T48	0	0	0	1
T49	0	3	0	1
T65	937	0	0	0
T73	1895	0	0	0
T74	4634	0	0	0
T75	1160	0	0	0
T76	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	149504	0	0
T4	1597	923	0	0
T5	1089	7	0	0
T6	994866	0	0	0
T7	0	352	0	0
T8	0	1032	0	0
T10	2699	0	0	0
T16	0	9433	0	0
T17	0	624	0	0
T25	1363	0	0	0
T26	1898	7	0	0
T31	0	7	0	0
T32	0	1070	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	354	0	0
T64	1959	0	0	0
T65	937	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	580574	0	312
T1	1819	130	0	0
T2	1786	195	0	0
T3	1790	127	0	0
T4	1597	912	0	0
T5	1089	526	0	0
T6	994866	1502	0	2
T10	2699	266	0	0
T15	0	0	0	2
T16	0	0	0	2
T24	1318	26	0	0
T25	1363	11	0	0
T26	1898	988	0	0
T36	0	0	0	2
T37	0	0	0	2
T54	0	0	0	2
T64	0	0	0	2
T69	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	2916	0	124
T7	786	0	0	0
T15	0	4	0	0
T21	0	3	0	1
T31	1898	0	0	0
T38	2273	4	0	0
T39	1899	0	0	0
T41	3438	3	0	1
T42	0	18	0	1
T44	3356	0	0	0
T47	0	3	0	1
T49	0	19	0	1
T50	0	0	0	1
T51	0	0	0	1
T65	937	0	0	0
T73	1895	0	0	0
T74	4634	0	0	0
T75	1160	0	0	0
T77	0	3	0	1
T78	0	7	0	1
T79	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	149504	0	0
T4	1597	923	0	0
T5	1089	7	0	0
T6	994866	0	0	0
T7	0	352	0	0
T8	0	1032	0	0
T10	2699	0	0	0
T16	0	9433	0	0
T17	0	624	0	0
T25	1363	0	0	0
T26	1898	7	0	0
T31	0	7	0	0
T32	0	1070	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	354	0	0
T64	1959	0	0	0
T65	937	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	580574	0	312
T1	1819	130	0	0
T2	1786	195	0	0
T3	1790	127	0	0
T4	1597	912	0	0
T5	1089	526	0	0
T6	994866	1502	0	2
T10	2699	266	0	0
T15	0	0	0	2
T16	0	0	0	2
T24	1318	26	0	0
T25	1363	11	0	0
T26	1898	988	0	0
T36	0	0	0	2
T37	0	0	0	2
T54	0	0	0	2
T64	0	0	0	2
T69	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	4234	0	117
T11	2012	0	0	0
T15	1906	0	0	0
T21	0	10	0	1
T22	0	3	0	1
T32	2063	0	0	0
T39	1899	0	0	0
T40	1589	0	0	0
T41	3438	3	0	1
T42	0	3	0	1
T47	0	53	0	1
T50	0	49	0	1
T51	0	34	0	1
T75	1160	0	0	0
T80	0	4	0	1
T81	0	4	0	1
T82	0	37	0	1
T83	2246	0	0	0
T84	2348	0	0	0
T85	1137	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	149504	0	0
T4	1597	923	0	0
T5	1089	7	0	0
T6	994866	0	0	0
T7	0	352	0	0
T8	0	1032	0	0
T10	2699	0	0	0
T16	0	9433	0	0
T17	0	624	0	0
T25	1363	0	0	0
T26	1898	7	0	0
T31	0	7	0	0
T32	0	1070	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	354	0	0
T64	1959	0	0	0
T65	937	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	580574	0	312
T1	1819	130	0	0
T2	1786	195	0	0
T3	1790	127	0	0
T4	1597	912	0	0
T5	1089	526	0	0
T6	994866	1502	0	2
T10	2699	266	0	0
T15	0	0	0	2
T16	0	0	0	2
T24	1318	26	0	0
T25	1363	11	0	0
T26	1898	988	0	0
T36	0	0	0	2
T37	0	0	0	2
T54	0	0	0	2
T64	0	0	0	2
T69	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	3751	0	115
T1	1819	4	0	1
T2	1786	4	0	1
T3	1790	0	0	0
T4	1597	0	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T10	2699	0	0	0
T21	0	17	0	1
T24	1318	3	0	1
T25	1363	0	0	0
T26	1898	1	0	0
T41	0	27	0	1
T42	0	3	0	1
T48	0	3	0	1
T50	0	20	0	1
T51	0	0	0	1
T86	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	149504	0	0
T4	1597	923	0	0
T5	1089	7	0	0
T6	994866	0	0	0
T7	0	352	0	0
T8	0	1032	0	0
T10	2699	0	0	0
T16	0	9433	0	0
T17	0	624	0	0
T25	1363	0	0	0
T26	1898	7	0	0
T31	0	7	0	0
T32	0	1070	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	354	0	0
T64	1959	0	0	0
T65	937	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	580574	0	312
T1	1819	130	0	0
T2	1786	195	0	0
T3	1790	127	0	0
T4	1597	912	0	0
T5	1089	526	0	0
T6	994866	1502	0	2
T10	2699	266	0	0
T15	0	0	0	2
T16	0	0	0	2
T24	1318	26	0	0
T25	1363	11	0	0
T26	1898	988	0	0
T36	0	0	0	2
T37	0	0	0	2
T54	0	0	0	2
T64	0	0	0	2
T69	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	4598	0	91
T4	1597	0	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T10	2699	0	0	0
T21	0	3	0	1
T22	0	3	0	1
T24	1318	28	0	1
T25	1363	0	0	0
T26	1898	0	0	0
T38	2273	0	0	0
T42	0	3	0	1
T43	0	3	0	1
T47	0	3	0	1
T50	0	3	0	1
T52	0	8	0	1
T64	1959	0	0	0
T65	937	0	0	0
T82	0	3	0	1
T87	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	149504	0	0
T4	1597	923	0	0
T5	1089	7	0	0
T6	994866	0	0	0
T7	0	352	0	0
T8	0	1032	0	0
T10	2699	0	0	0
T16	0	9433	0	0
T17	0	624	0	0
T25	1363	0	0	0
T26	1898	7	0	0
T31	0	7	0	0
T32	0	1070	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	354	0	0
T64	1959	0	0	0
T65	937	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	580574	0	312
T1	1819	130	0	0
T2	1786	195	0	0
T3	1790	127	0	0
T4	1597	912	0	0
T5	1089	526	0	0
T6	994866	1502	0	2
T10	2699	266	0	0
T15	0	0	0	2
T16	0	0	0	2
T24	1318	26	0	0
T25	1363	11	0	0
T26	1898	988	0	0
T36	0	0	0	2
T37	0	0	0	2
T54	0	0	0	2
T64	0	0	0	2
T69	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	2152	0	85
T5	1089	1	0	0
T6	994866	0	0	0
T7	786	0	0	0
T21	0	3	0	1
T22	0	62	0	1
T25	1363	0	0	0
T26	1898	0	0	0
T38	2273	0	0	0
T41	0	40	0	1
T42	0	3	0	1
T43	0	3	0	1
T44	3356	0	0	0
T47	0	3	0	1
T48	0	22	0	1
T53	0	0	0	1
T54	0	4	0	0
T64	1959	0	0	0
T65	937	0	0	0
T73	1895	0	0	0
T82	0	0	0	1
T88	0	11	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	149504	0	0
T4	1597	923	0	0
T5	1089	7	0	0
T6	994866	0	0	0
T7	0	352	0	0
T8	0	1032	0	0
T10	2699	0	0	0
T16	0	9433	0	0
T17	0	624	0	0
T25	1363	0	0	0
T26	1898	7	0	0
T31	0	7	0	0
T32	0	1070	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	354	0	0
T64	1959	0	0	0
T65	937	0	0	0