Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	234573940	10443886	0	0
boot_gen_cmd_rd_A	234573940	39419	0	0
boot_ins_cmd_rd_A	234573940	45360	0	0
ctrl_rd_A	234573940	38832	0	0
err_code_test_rd_A	234573940	44685	0	0
intr_enable_rd_A	234573940	44877	0	0
max_num_reqs_between_reseeds_rd_A	234573940	39549	0	0
regwen_rd_A	234573940	45280	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	10443886	0	0
T6	994866	566210	0	0
T7	786	0	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T36	0	449139	0	0
T37	0	430193	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T64	1959	0	0	0
T65	937	0	0	0
T73	1895	0	0	0
T74	4634	0	0	0
T232	0	155462	0	0
T233	0	273191	0	0
T234	0	151590	0	0
T235	0	312326	0	0
T236	0	219402	0	0
T237	0	52435	0	0
T238	0	47613	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	39419	0	0
T14	4073	0	0	0
T18	43000	0	0	0
T27	1445	0	0	0
T107	2604	0	0	0
T163	2012	0	0	0
T197	683	0	0	0
T237	140954	851	0	0
T238	0	1498	0	0
T239	0	5251	0	0
T240	0	2124	0	0
T241	0	3567	0	0
T242	0	8193	0	0
T243	0	3481	0	0
T244	0	906	0	0
T245	0	1745	0	0
T246	0	962	0	0
T247	1150	0	0	0
T248	7725	0	0	0
T249	6802	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	45360	0	0
T14	4073	0	0	0
T18	43000	0	0	0
T27	1445	0	0	0
T107	2604	0	0	0
T163	2012	0	0	0
T197	683	0	0	0
T237	140954	892	0	0
T238	0	1659	0	0
T239	0	5997	0	0
T240	0	2315	0	0
T241	0	3774	0	0
T242	0	9766	0	0
T243	0	3730	0	0
T244	0	1027	0	0
T245	0	2170	0	0
T246	0	1180	0	0
T247	1150	0	0	0
T248	7725	0	0	0
T249	6802	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	38832	0	0
T29	0	2	0	0
T113	858	0	0	0
T195	2551	0	0	0
T199	1403	0	0	0
T226	2783	9	0	0
T232	391002	0	0	0
T233	492385	0	0	0
T237	0	709	0	0
T238	0	1485	0	0
T239	0	5228	0	0
T240	0	1899	0	0
T241	0	3410	0	0
T250	0	5	0	0
T251	0	8	0	0
T252	0	5	0	0
T253	2500	0	0	0
T254	2987	0	0	0
T255	1584	0	0	0
T256	1221	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	44685	0	0
T14	4073	0	0	0
T18	43000	0	0	0
T27	1445	0	0	0
T107	2604	0	0	0
T163	2012	0	0	0
T197	683	0	0	0
T237	140954	1096	0	0
T238	0	1746	0	0
T239	0	6405	0	0
T240	0	2108	0	0
T241	0	3907	0	0
T242	0	9212	0	0
T243	0	3666	0	0
T244	0	987	0	0
T245	0	1940	0	0
T246	0	1132	0	0
T247	1150	0	0	0
T248	7725	0	0	0
T249	6802	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	44877	0	0
T9	836	0	0	0
T21	3414	0	0	0
T57	10409	15	0	0
T77	1329	0	0	0
T78	1916	0	0	0
T79	900	0	0	0
T96	0	66	0	0
T102	3420	0	0	0
T105	2573	0	0	0
T196	655	0	0	0
T237	0	1049	0	0
T238	0	1748	0	0
T239	0	5540	0	0
T240	0	2261	0	0
T241	0	3594	0	0
T252	0	63	0	0
T257	0	42	0	0
T258	0	143	0	0
T259	3369	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	39549	0	0
T14	4073	0	0	0
T18	43000	0	0	0
T27	1445	0	0	0
T107	2604	0	0	0
T163	2012	0	0	0
T197	683	0	0	0
T237	140954	901	0	0
T238	0	1451	0	0
T239	0	5454	0	0
T240	0	1872	0	0
T241	0	3458	0	0
T242	0	8198	0	0
T243	0	3292	0	0
T244	0	1061	0	0
T245	0	1901	0	0
T246	0	791	0	0
T247	1150	0	0	0
T248	7725	0	0	0
T249	6802	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234573940	45280	0	0
T14	4073	0	0	0
T18	43000	0	0	0
T27	1445	0	0	0
T107	2604	0	0	0
T163	2012	0	0	0
T197	683	0	0	0
T237	140954	955	0	0
T238	0	1551	0	0
T239	0	6061	0	0
T240	0	2290	0	0
T241	0	4121	0	0
T242	0	9252	0	0
T243	0	3976	0	0
T244	0	1032	0	0
T245	0	1948	0	0
T246	0	1010	0	0
T247	1150	0	0	0
T248	7725	0	0	0
T249	6802	0	0	0