Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	98.25	93.97	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.23	99.92	92.75	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T26,T11

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T20
1	0	Covered	T5,T29,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T23,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T24,T4	Yes	T3,T24,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T24	Yes	T2,T3,T24	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T24	Yes	T2,T3,T24	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T12,T40	Yes	T1,T12,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T24,T12	Yes	T1,T24,T12	INPUT
edn_i[3].edn_req	Yes	Yes	T24,T40,T16	Yes	T24,T40,T16	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T15,T40	Yes	T1,T15,T40	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T3,T24	Yes	T1,T3,T24	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T24,T41	Yes	T1,T24,T41	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T12,T42	Yes	T1,T12,T40	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T12,T43,T44	Yes	T1,T12,T42	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T12,T40	Yes	T1,T12,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T24,T12	Yes	T1,T24,T12	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T5,T45	Yes	T1,T24,T12	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T24,T12	Yes	T1,T24,T12	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T24,T40,T42	Yes	T24,T40,T42	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T40,T42,T31	Yes	T40,T42,T31	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T24,T40,T42	Yes	T24,T40,T42	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T15,T40	Yes	T1,T15,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T15,T40	Yes	T1,T15,T40	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T15,T40	Yes	T1,T15,T40	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T3,T24	Yes	T1,T3,T24	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T3,T24,T40	Yes	T1,T3,T24	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T3,T24	Yes	T1,T3,T24	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T24,T41	Yes	T1,T24,T41	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T1,T21,T46	Yes	T1,T24,T40	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T24,T41	Yes	T1,T24,T41	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T26,T47,T48	Yes	T26,T47,T48	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T26,T11	Yes	T3,T26,T11	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T49,T29	Yes	T5,T49,T29	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T26,T11	Yes	T3,T26,T11	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T49,T29	Yes	T5,T49,T29	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T6,T50	Yes	T4,T6,T50	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	191912577	191732954	0	0
CsrngAppIfOut_A	191912577	191732954	0	0
FpvSecCmCntAlertCheck_A	191912577	116	0	0
FpvSecCmGenCmdFifoRptrCheck_A	191912577	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	191912577	70	0	0
FpvSecCmMainFsmCheck_A	191912577	70	0	0
FpvSecCmRegWeOnehotCheck_A	191912577	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	191912577	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	191912577	70	0	0
IntrEdnCmdReqDoneKnownO_A	191912577	191732954	0	0
TlAReadyKnownO_A	191912577	191732954	0	0
TlDValidKnownO_A	191912577	191732954	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	191912577	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	191912577	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	191912577	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	191912577	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	191912577	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	191912577	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	191912577	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	191912577	600593	0	314
gen_edn_if_asserts[0].EdnDataStable_A	191912577	126190	0	437
gen_edn_if_asserts[0].EdnEndPointOut_A	191912577	191732954	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	191912577	155580	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	191912577	600593	0	314
gen_edn_if_asserts[1].EdnDataStable_A	191912577	4039	0	136
gen_edn_if_asserts[1].EdnEndPointOut_A	191912577	191732954	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	191912577	155580	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	191912577	600593	0	314
gen_edn_if_asserts[2].EdnDataStable_A	191912577	9028	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	191912577	191732954	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	191912577	155580	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	191912577	600593	0	314
gen_edn_if_asserts[3].EdnDataStable_A	191912577	3514	0	105
gen_edn_if_asserts[3].EdnEndPointOut_A	191912577	191732954	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	191912577	155580	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	191912577	600593	0	314
gen_edn_if_asserts[4].EdnDataStable_A	191912577	4221	0	91
gen_edn_if_asserts[4].EdnEndPointOut_A	191912577	191732954	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	191912577	155580	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	191912577	600593	0	314
gen_edn_if_asserts[5].EdnDataStable_A	191912577	2674	0	96
gen_edn_if_asserts[5].EdnEndPointOut_A	191912577	191732954	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	191912577	155580	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	191912577	600593	0	314
gen_edn_if_asserts[6].EdnDataStable_A	191912577	2333	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	191912577	191732954	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	191912577	155580	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	116	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	10	0	0
T42	2073	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	70	0	0
T7	2270	0	0	0
T16	27785	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T42	2073	0	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T64	0	10	0	0
T65	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	600593	0	314
T1	2859	37	0	0
T2	2292	40	0	0
T3	2500	193	0	0
T4	19558	2576	0	0
T10	4049	54	0	0
T11	2148	228	0	0
T15	0	0	0	2
T16	0	0	0	2
T22	0	0	0	2
T23	1760	33	0	0
T24	3999	19	0	0
T25	2410	22	0	0
T26	1856	195	0	0
T37	0	0	0	2
T49	0	0	0	2
T50	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	126190	0	437
T1	2859	41	0	1
T2	2292	37	0	1
T3	2500	4	0	1
T4	19558	26	0	1
T10	4049	159	0	1
T11	2148	4	0	1
T23	1760	3	0	1
T24	3999	3	0	1
T25	2410	3	0	1
T26	1856	4	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	155580	0	0
T5	2055	20	0	0
T6	6289	0	0	0
T7	0	1103	0	0
T15	2802	0	0	0
T16	0	10072	0	0
T17	0	634	0	0
T29	0	42	0	0
T31	0	7	0	0
T32	0	202	0	0
T40	4017	0	0	0
T45	1775	0	0	0
T49	1055	0	0	0
T50	11513	0	0	0
T67	0	1112	0	0
T68	0	233	0	0
T69	0	1119	0	0
T70	3052	0	0	0
T71	3248	0	0	0
T72	1507	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	600593	0	314
T1	2859	37	0	0
T2	2292	40	0	0
T3	2500	193	0	0
T4	19558	2576	0	0
T10	4049	54	0	0
T11	2148	228	0	0
T15	0	0	0	2
T16	0	0	0	2
T22	0	0	0	2
T23	1760	33	0	0
T24	3999	19	0	0
T25	2410	22	0	0
T26	1856	195	0	0
T37	0	0	0	2
T49	0	0	0	2
T50	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	4039	0	136
T1	2859	3	0	1
T2	2292	0	0	0
T3	2500	0	0	0
T4	19558	0	0	0
T10	4049	0	0	0
T11	2148	0	0	0
T12	0	15	0	1
T23	1760	0	0	0
T24	3999	0	0	0
T25	2410	0	0	0
T26	1856	0	0	0
T40	0	3	0	1
T42	0	3	0	1
T43	0	0	0	1
T61	0	4	0	0
T73	0	20	0	1
T74	0	3	0	1
T75	0	11	0	1
T76	0	3	0	1
T77	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	155580	0	0
T5	2055	20	0	0
T6	6289	0	0	0
T7	0	1103	0	0
T15	2802	0	0	0
T16	0	10072	0	0
T17	0	634	0	0
T29	0	42	0	0
T31	0	7	0	0
T32	0	202	0	0
T40	4017	0	0	0
T45	1775	0	0	0
T49	1055	0	0	0
T50	11513	0	0	0
T67	0	1112	0	0
T68	0	233	0	0
T69	0	1119	0	0
T70	3052	0	0	0
T71	3248	0	0	0
T72	1507	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	600593	0	314
T1	2859	37	0	0
T2	2292	40	0	0
T3	2500	193	0	0
T4	19558	2576	0	0
T10	4049	54	0	0
T11	2148	228	0	0
T15	0	0	0	2
T16	0	0	0	2
T22	0	0	0	2
T23	1760	33	0	0
T24	3999	19	0	0
T25	2410	22	0	0
T26	1856	195	0	0
T37	0	0	0	2
T49	0	0	0	2
T50	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	9028	0	127
T1	2859	13	0	1
T2	2292	0	0	0
T3	2500	0	0	0
T4	19558	0	0	0
T5	0	1	0	0
T10	4049	0	0	0
T11	2148	0	0	0
T12	0	18	0	1
T23	1760	0	0	0
T24	3999	3	0	1
T25	2410	0	0	0
T26	1856	0	0	0
T40	0	62	0	1
T42	0	3	0	1
T45	0	47	0	1
T58	0	3	0	1
T60	0	3	0	1
T78	0	4	0	1
T79	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	155580	0	0
T5	2055	20	0	0
T6	6289	0	0	0
T7	0	1103	0	0
T15	2802	0	0	0
T16	0	10072	0	0
T17	0	634	0	0
T29	0	42	0	0
T31	0	7	0	0
T32	0	202	0	0
T40	4017	0	0	0
T45	1775	0	0	0
T49	1055	0	0	0
T50	11513	0	0	0
T67	0	1112	0	0
T68	0	233	0	0
T69	0	1119	0	0
T70	3052	0	0	0
T71	3248	0	0	0
T72	1507	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	600593	0	314
T1	2859	37	0	0
T2	2292	40	0	0
T3	2500	193	0	0
T4	19558	2576	0	0
T10	4049	54	0	0
T11	2148	228	0	0
T15	0	0	0	2
T16	0	0	0	2
T22	0	0	0	2
T23	1760	33	0	0
T24	3999	19	0	0
T25	2410	22	0	0
T26	1856	195	0	0
T37	0	0	0	2
T49	0	0	0	2
T50	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	3514	0	105
T4	19558	0	0	0
T5	2055	0	0	0
T6	6289	0	0	0
T11	2148	0	0	0
T12	2217	0	0	0
T24	3999	3	0	1
T25	2410	0	0	0
T26	1856	0	0	0
T31	0	1	0	0
T40	0	12	0	1
T41	1002	0	0	0
T42	0	61	0	1
T43	0	0	0	1
T73	0	3	0	1
T74	0	62	0	1
T75	0	17	0	1
T79	0	3	0	1
T80	0	4	0	1
T81	0	4	0	0
T82	2246	0	0	0
T83	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	155580	0	0
T5	2055	20	0	0
T6	6289	0	0	0
T7	0	1103	0	0
T15	2802	0	0	0
T16	0	10072	0	0
T17	0	634	0	0
T29	0	42	0	0
T31	0	7	0	0
T32	0	202	0	0
T40	4017	0	0	0
T45	1775	0	0	0
T49	1055	0	0	0
T50	11513	0	0	0
T67	0	1112	0	0
T68	0	233	0	0
T69	0	1119	0	0
T70	3052	0	0	0
T71	3248	0	0	0
T72	1507	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	600593	0	314
T1	2859	37	0	0
T2	2292	40	0	0
T3	2500	193	0	0
T4	19558	2576	0	0
T10	4049	54	0	0
T11	2148	228	0	0
T15	0	0	0	2
T16	0	0	0	2
T22	0	0	0	2
T23	1760	33	0	0
T24	3999	19	0	0
T25	2410	22	0	0
T26	1856	195	0	0
T37	0	0	0	2
T49	0	0	0	2
T50	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	4221	0	91
T1	2859	62	0	1
T2	2292	0	0	0
T3	2500	0	0	0
T4	19558	0	0	0
T10	4049	0	0	0
T11	2148	0	0	0
T15	0	8	0	0
T21	0	6	0	1
T23	1760	0	0	0
T24	3999	0	0	0
T25	2410	0	0	0
T26	1856	0	0	0
T40	0	25	0	1
T58	0	3	0	1
T73	0	62	0	1
T74	0	51	0	1
T75	0	0	0	1
T76	0	0	0	1
T79	0	43	0	1
T84	0	4	0	0
T85	0	39	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	155580	0	0
T5	2055	20	0	0
T6	6289	0	0	0
T7	0	1103	0	0
T15	2802	0	0	0
T16	0	10072	0	0
T17	0	634	0	0
T29	0	42	0	0
T31	0	7	0	0
T32	0	202	0	0
T40	4017	0	0	0
T45	1775	0	0	0
T49	1055	0	0	0
T50	11513	0	0	0
T67	0	1112	0	0
T68	0	233	0	0
T69	0	1119	0	0
T70	3052	0	0	0
T71	3248	0	0	0
T72	1507	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	600593	0	314
T1	2859	37	0	0
T2	2292	40	0	0
T3	2500	193	0	0
T4	19558	2576	0	0
T10	4049	54	0	0
T11	2148	228	0	0
T15	0	0	0	2
T16	0	0	0	2
T22	0	0	0	2
T23	1760	33	0	0
T24	3999	19	0	0
T25	2410	22	0	0
T26	1856	195	0	0
T37	0	0	0	2
T49	0	0	0	2
T50	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	2674	0	96
T1	2859	7	0	1
T2	2292	0	0	0
T3	2500	4	0	0
T4	19558	0	0	0
T10	4049	0	0	0
T11	2148	0	0	0
T21	0	3	0	1
T22	0	4	0	0
T23	1760	0	0	0
T24	3999	32	0	1
T25	2410	0	0	0
T26	1856	0	0	0
T40	0	58	0	1
T73	0	3	0	1
T74	0	3	0	1
T75	0	0	0	1
T76	0	0	0	1
T86	0	3	0	1
T87	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	155580	0	0
T5	2055	20	0	0
T6	6289	0	0	0
T7	0	1103	0	0
T15	2802	0	0	0
T16	0	10072	0	0
T17	0	634	0	0
T29	0	42	0	0
T31	0	7	0	0
T32	0	202	0	0
T40	4017	0	0	0
T45	1775	0	0	0
T49	1055	0	0	0
T50	11513	0	0	0
T67	0	1112	0	0
T68	0	233	0	0
T69	0	1119	0	0
T70	3052	0	0	0
T71	3248	0	0	0
T72	1507	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	600593	0	314
T1	2859	37	0	0
T2	2292	40	0	0
T3	2500	193	0	0
T4	19558	2576	0	0
T10	4049	54	0	0
T11	2148	228	0	0
T15	0	0	0	2
T16	0	0	0	2
T22	0	0	0	2
T23	1760	33	0	0
T24	3999	19	0	0
T25	2410	22	0	0
T26	1856	195	0	0
T37	0	0	0	2
T49	0	0	0	2
T50	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T66	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	2333	0	79
T1	2859	33	0	1
T2	2292	0	0	0
T3	2500	0	0	0
T4	19558	0	0	0
T10	4049	0	0	0
T11	2148	0	0	0
T21	0	36	0	1
T22	0	4	0	0
T23	1760	0	0	0
T24	3999	3	0	1
T25	2410	0	0	0
T26	1856	0	0	0
T40	0	3	0	1
T41	0	3	0	1
T43	0	3	0	1
T73	0	3	0	1
T75	0	3	0	1
T88	0	4	0	0
T89	0	0	0	1
T90	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	155580	0	0
T5	2055	20	0	0
T6	6289	0	0	0
T7	0	1103	0	0
T15	2802	0	0	0
T16	0	10072	0	0
T17	0	634	0	0
T29	0	42	0	0
T31	0	7	0	0
T32	0	202	0	0
T40	4017	0	0	0
T45	1775	0	0	0
T49	1055	0	0	0
T50	11513	0	0	0
T67	0	1112	0	0
T68	0	233	0	0
T69	0	1119	0	0
T70	3052	0	0	0
T71	3248	0	0	0
T72	1507	0	0	0