Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	192403564	8342623	0	0
boot_gen_cmd_rd_A	192403564	67507	0	0
boot_ins_cmd_rd_A	192403564	78099	0	0
ctrl_rd_A	192403564	67702	0	0
err_code_test_rd_A	192403564	77220	0	0
intr_enable_rd_A	192403564	76489	0	0
max_num_reqs_between_reseeds_rd_A	192403564	69232	0	0
regwen_rd_A	192403564	76923	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	8342623	0	0
T31	1122	0	0	0
T32	518	0	0	0
T37	603016	329836	0	0
T38	0	60244	0	0
T39	0	230277	0	0
T67	1890	0	0	0
T73	3755	0	0	0
T80	2570	0	0	0
T84	1167	0	0	0
T87	2274	0	0	0
T99	0	79238	0	0
T102	0	179745	0	0
T105	2562	0	0	0
T164	1209	0	0	0
T229	0	99705	0	0
T230	0	37127	0	0
T231	0	265824	0	0
T232	0	185593	0	0
T233	0	191881	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	67507	0	0
T18	2263	0	0	0
T39	658550	6973	0	0
T46	8368	0	0	0
T51	2037	0	0	0
T95	1465	0	0	0
T107	2267	0	0	0
T229	0	1556	0	0
T230	0	960	0	0
T231	0	3758	0	0
T232	0	5488	0	0
T234	0	6757	0	0
T235	0	1727	0	0
T236	0	2211	0	0
T237	0	1447	0	0
T238	0	5648	0	0
T239	5647	0	0	0
T240	3445	0	0	0
T241	2505	0	0	0
T242	5171	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	78099	0	0
T18	2263	0	0	0
T39	658550	8123	0	0
T46	8368	0	0	0
T51	2037	0	0	0
T95	1465	0	0	0
T107	2267	0	0	0
T229	0	1747	0	0
T230	0	1177	0	0
T231	0	4959	0	0
T232	0	6506	0	0
T234	0	7675	0	0
T235	0	2113	0	0
T236	0	2243	0	0
T237	0	1690	0	0
T238	0	6281	0	0
T239	5647	0	0	0
T240	3445	0	0	0
T241	2505	0	0	0
T242	5171	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	67702	0	0
T22	2015	0	0	0
T28	0	5	0	0
T39	0	6885	0	0
T66	1121	0	0	0
T68	689	0	0	0
T74	2639	0	0	0
T75	7302	0	0	0
T76	3967	0	0	0
T77	1177	0	0	0
T80	2570	3	0	0
T81	1149	0	0	0
T85	3735	0	0	0
T127	0	2	0	0
T229	0	1646	0	0
T230	0	1087	0	0
T231	0	4098	0	0
T232	0	5805	0	0
T243	0	3	0	0
T244	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	77220	0	0
T18	2263	0	0	0
T39	658550	7931	0	0
T46	8368	0	0	0
T51	2037	0	0	0
T95	1465	0	0	0
T107	2267	0	0	0
T229	0	1684	0	0
T230	0	1060	0	0
T231	0	4614	0	0
T232	0	6011	0	0
T234	0	7892	0	0
T235	0	1995	0	0
T236	0	2608	0	0
T237	0	1456	0	0
T238	0	6703	0	0
T239	5647	0	0	0
T240	3445	0	0	0
T241	2505	0	0	0
T242	5171	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	76489	0	0
T18	2263	0	0	0
T39	658550	7102	0	0
T46	8368	0	0	0
T51	2037	0	0	0
T95	1465	0	0	0
T107	2267	0	0	0
T229	0	1911	0	0
T230	0	1332	0	0
T231	0	3774	0	0
T232	0	6104	0	0
T234	0	7145	0	0
T235	0	1942	0	0
T239	5647	0	0	0
T240	3445	0	0	0
T241	2505	0	0	0
T242	5171	0	0	0
T245	0	22	0	0
T246	0	73	0	0
T247	0	40	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	69232	0	0
T18	2263	0	0	0
T39	658550	7043	0	0
T46	8368	0	0	0
T51	2037	0	0	0
T95	1465	0	0	0
T107	2267	0	0	0
T229	0	1508	0	0
T230	0	1115	0	0
T231	0	4376	0	0
T232	0	5326	0	0
T234	0	6675	0	0
T235	0	1771	0	0
T236	0	2193	0	0
T237	0	1445	0	0
T238	0	5982	0	0
T239	5647	0	0	0
T240	3445	0	0	0
T241	2505	0	0	0
T242	5171	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192403564	76923	0	0
T18	2263	0	0	0
T39	658550	7399	0	0
T46	8368	0	0	0
T51	2037	0	0	0
T95	1465	0	0	0
T107	2267	0	0	0
T229	0	1754	0	0
T230	0	1149	0	0
T231	0	4916	0	0
T232	0	6037	0	0
T234	0	7462	0	0
T235	0	1835	0	0
T236	0	2599	0	0
T237	0	1727	0	0
T238	0	6314	0	0
T239	5647	0	0	0
T240	3445	0	0	0
T241	2505	0	0	0
T242	5171	0	0	0