Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.17	98.25	93.73	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.07	99.92	92.41	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T10,T31

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T4,T5,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T24,T10	Yes	T1,T24,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T24	Yes	T1,T2,T24	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T4,T10	Yes	T3,T4,T10	INPUT
edn_i[1].edn_req	Yes	Yes	T24,T11,T30	Yes	T24,T11,T30	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T11,T30	Yes	T1,T11,T30	INPUT
edn_i[3].edn_req	Yes	Yes	T11,T30,T41	Yes	T11,T30,T41	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T30,T42	Yes	T2,T30,T42	INPUT
edn_i[5].edn_req	Yes	Yes	T29,T30,T43	Yes	T29,T30,T43	INPUT
edn_i[6].edn_req	Yes	Yes	T14,T30,T44	Yes	T14,T30,T44	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T10,T45	Yes	T3,T10,T45	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T10,T46,T47	Yes	T3,T10,T45	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T4,T10	Yes	T3,T4,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T24,T11,T47	Yes	T24,T11,T30	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T24,T48,T12	Yes	T24,T30,T47	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T24,T11,T30	Yes	T24,T11,T30	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T11,T30	Yes	T1,T11,T30	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T11,T30,T42	Yes	T11,T30,T42	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T11,T30	Yes	T1,T11,T30	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T11,T30,T41	Yes	T11,T30,T41	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T30,T41,T49	Yes	T30,T41,T49	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T11,T30,T41	Yes	T11,T30,T41	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T30,T42	Yes	T2,T30,T42	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T47,T50,T51	Yes	T2,T30,T47	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T30,T42	Yes	T2,T30,T42	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T29,T30,T52	Yes	T29,T30,T43	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T53,T54,T55	Yes	T52,T47,T56	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T29,T30,T43	Yes	T29,T30,T43	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T14,T30,T44	Yes	T14,T30,T44	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T30,T43,T57	Yes	T30,T43,T47	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T14,T30,T44	Yes	T14,T30,T44	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T24,T14	Yes	T24,T10,T14	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T24,T10,T11	Yes	T24,T14,T11	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T29,T42,T58	Yes	T29,T42,T58	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T10,T25	Yes	T1,T10,T25	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T25,T26	Yes	T4,T25,T26	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T10,T25	Yes	T1,T10,T25	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T25,T26	Yes	T4,T25,T26	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T15,T38	Yes	T4,T15,T38	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	11672832	11508162	0	0
CsrngAppIfOut_A	11672832	11508162	0	0
FpvSecCmCntAlertCheck_A	11672832	100	0	0
FpvSecCmGenCmdFifoRptrCheck_A	11672832	60	0	0
FpvSecCmGenCmdFifoWptrCheck_A	11672832	60	0	0
FpvSecCmMainFsmCheck_A	11672832	60	0	0
FpvSecCmRegWeOnehotCheck_A	11672832	60	0	0
FpvSecCmResCmdFifoRptrCheck_A	11672832	60	0	0
FpvSecCmResCmdFifoWptrCheck_A	11672832	60	0	0
IntrEdnCmdReqDoneKnownO_A	11672832	11508162	0	0
TlAReadyKnownO_A	11672832	11508162	0	0
TlDValidKnownO_A	11672832	11508162	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	11672832	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	11672832	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	11672832	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	11672832	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	11672832	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	11672832	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	11672832	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	11672832	577130	0	292
gen_edn_if_asserts[0].EdnDataStable_A	11672832	27029	0	437
gen_edn_if_asserts[0].EdnEndPointOut_A	11672832	11508162	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	11672832	150196	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	11672832	577130	0	292
gen_edn_if_asserts[1].EdnDataStable_A	11672832	53991	0	123
gen_edn_if_asserts[1].EdnEndPointOut_A	11672832	11508162	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	11672832	150196	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	11672832	577130	0	292
gen_edn_if_asserts[2].EdnDataStable_A	11672832	2266	0	114
gen_edn_if_asserts[2].EdnEndPointOut_A	11672832	11508162	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	11672832	150196	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	11672832	577130	0	292
gen_edn_if_asserts[3].EdnDataStable_A	11672832	4395	0	92
gen_edn_if_asserts[3].EdnEndPointOut_A	11672832	11508162	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	11672832	150196	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	11672832	577130	0	292
gen_edn_if_asserts[4].EdnDataStable_A	11672832	4226	0	110
gen_edn_if_asserts[4].EdnEndPointOut_A	11672832	11508162	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	11672832	150196	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	11672832	577130	0	292
gen_edn_if_asserts[5].EdnDataStable_A	11672832	1288	0	84
gen_edn_if_asserts[5].EdnEndPointOut_A	11672832	11508162	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	11672832	150196	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	11672832	577130	0	292
gen_edn_if_asserts[6].EdnDataStable_A	11672832	2564	0	83
gen_edn_if_asserts[6].EdnEndPointOut_A	11672832	11508162	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	11672832	150196	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	100	0	0
T8	0	1	0	0
T15	1440	1	0	0
T16	1093	1	0	0
T17	0	1	0	0
T18	0	10	0	0
T38	223555	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	939	0	0	0
T65	5112	0	0	0
T66	942	0	0	0
T67	1342	0	0	0
T68	1637	0	0	0
T69	1864	0	0	0
T70	1065	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	60	0	0
T18	27361	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T71	0	10	0	0
T72	0	10	0	0
T73	1335	0	0	0
T74	2498	0	0	0
T75	11079	0	0	0
T76	521607	0	0	0
T77	1778	0	0	0
T78	2785	0	0	0
T79	1015	0	0	0
T80	1676	0	0	0
T81	3013	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	577130	0	292
T1	2219	133	0	0
T2	3527	1112	0	2
T3	1965	504	0	0
T4	2004	1054	0	0
T10	2346	133	0	0
T11	2329	60	0	0
T14	2456	1510	0	2
T24	2003	46	0	0
T25	1460	1360	0	2
T26	1521	1463	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	27029	0	437
T3	1965	3	0	1
T4	2004	1	0	0
T10	2346	8	0	1
T11	2329	0	0	0
T14	2456	0	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T29	0	4	0	1
T30	0	3	0	1
T31	0	4	0	1
T45	1264	3	0	1
T46	0	33	0	1
T58	0	0	0	1
T82	1181	0	0	0
T85	0	3	0	1
T86	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	150196	0	0
T4	2004	7	0	0
T5	0	655	0	0
T6	0	612	0	0
T7	0	1160	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T15	0	652	0	0
T16	0	604	0	0
T17	0	600	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T33	0	7	0	0
T45	1264	0	0	0
T66	0	452	0	0
T82	1181	0	0	0
T85	1478	0	0	0
T87	0	1134	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	577130	0	292
T1	2219	133	0	0
T2	3527	1112	0	2
T3	1965	504	0	0
T4	2004	1054	0	0
T10	2346	133	0	0
T11	2329	60	0	0
T14	2456	1510	0	2
T24	2003	46	0	0
T25	1460	1360	0	2
T26	1521	1463	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	53991	0	123
T10	2346	0	0	0
T11	2329	3	0	1
T14	2456	0	0	0
T22	0	4	0	0
T24	2003	15	0	1
T25	1460	0	0	0
T26	1521	0	0	0
T30	0	3	0	1
T31	2857	0	0	0
T43	0	3	0	1
T45	1264	0	0	0
T47	0	3	0	1
T48	0	64	0	1
T74	0	3	0	1
T77	0	3	0	1
T82	1181	0	0	0
T85	1478	0	0	0
T88	0	3	0	1
T89	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	150196	0	0
T4	2004	7	0	0
T5	0	655	0	0
T6	0	612	0	0
T7	0	1160	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T15	0	652	0	0
T16	0	604	0	0
T17	0	600	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T33	0	7	0	0
T45	1264	0	0	0
T66	0	452	0	0
T82	1181	0	0	0
T85	1478	0	0	0
T87	0	1134	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	577130	0	292
T1	2219	133	0	0
T2	3527	1112	0	2
T3	1965	504	0	0
T4	2004	1054	0	0
T10	2346	133	0	0
T11	2329	60	0	0
T14	2456	1510	0	2
T24	2003	46	0	0
T25	1460	1360	0	2
T26	1521	1463	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	2266	0	114
T1	2219	4	0	1
T2	3527	0	0	0
T3	1965	0	0	0
T4	2004	0	0	0
T10	2346	0	0	0
T11	2329	72	0	1
T14	2456	0	0	0
T17	0	1	0	0
T21	0	4	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T30	0	16	0	1
T42	0	4	0	0
T43	0	3	0	1
T47	0	3	0	1
T53	0	0	0	1
T74	0	4	0	1
T79	0	3	0	1
T90	0	0	0	1
T91	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	150196	0	0
T4	2004	7	0	0
T5	0	655	0	0
T6	0	612	0	0
T7	0	1160	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T15	0	652	0	0
T16	0	604	0	0
T17	0	600	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T33	0	7	0	0
T45	1264	0	0	0
T66	0	452	0	0
T82	1181	0	0	0
T85	1478	0	0	0
T87	0	1134	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	577130	0	292
T1	2219	133	0	0
T2	3527	1112	0	2
T3	1965	504	0	0
T4	2004	1054	0	0
T10	2346	133	0	0
T11	2329	60	0	0
T14	2456	1510	0	2
T24	2003	46	0	0
T25	1460	1360	0	2
T26	1521	1463	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	4395	0	92
T11	2329	3	0	1
T26	1521	0	0	0
T29	2351	0	0	0
T30	2211	29	0	1
T31	2857	0	0	0
T41	0	4	0	0
T42	2299	0	0	0
T45	1264	0	0	0
T47	0	3	0	1
T49	0	4	0	0
T55	0	0	0	1
T78	0	19	0	1
T82	1181	0	0	0
T83	734	0	0	0
T85	1478	0	0	0
T88	0	30	0	1
T92	0	4	0	1
T93	0	19	0	1
T94	0	4	0	0
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	150196	0	0
T4	2004	7	0	0
T5	0	655	0	0
T6	0	612	0	0
T7	0	1160	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T15	0	652	0	0
T16	0	604	0	0
T17	0	600	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T33	0	7	0	0
T45	1264	0	0	0
T66	0	452	0	0
T82	1181	0	0	0
T85	1478	0	0	0
T87	0	1134	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	577130	0	292
T1	2219	133	0	0
T2	3527	1112	0	2
T3	1965	504	0	0
T4	2004	1054	0	0
T10	2346	133	0	0
T11	2329	60	0	0
T14	2456	1510	0	2
T24	2003	46	0	0
T25	1460	1360	0	2
T26	1521	1463	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	4226	0	110
T2	3527	4	0	0
T3	1965	0	0	0
T4	2004	0	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T30	0	3	0	1
T42	0	4	0	1
T43	0	3	0	1
T45	1264	0	0	0
T47	0	52	0	1
T50	0	0	0	1
T74	0	12	0	1
T80	0	7	0	1
T88	0	3	0	1
T97	0	3	0	1
T98	0	4	0	0
T99	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	150196	0	0
T4	2004	7	0	0
T5	0	655	0	0
T6	0	612	0	0
T7	0	1160	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T15	0	652	0	0
T16	0	604	0	0
T17	0	600	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T33	0	7	0	0
T45	1264	0	0	0
T66	0	452	0	0
T82	1181	0	0	0
T85	1478	0	0	0
T87	0	1134	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	577130	0	292
T1	2219	133	0	0
T2	3527	1112	0	2
T3	1965	504	0	0
T4	2004	1054	0	0
T10	2346	133	0	0
T11	2329	60	0	0
T14	2456	1510	0	2
T24	2003	46	0	0
T25	1460	1360	0	2
T26	1521	1463	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	1288	0	84
T29	2351	4	0	0
T30	2211	3	0	1
T41	1167	0	0	0
T42	2299	0	0	0
T43	0	3	0	1
T44	1936	0	0	0
T46	1526	0	0	0
T47	0	3	0	1
T51	0	3	0	1
T52	0	3	0	1
T53	0	11	0	1
T54	0	3	0	1
T56	0	4	0	1
T58	1535	0	0	0
T84	880	0	0	0
T86	1025	0	0	0
T92	2182	0	0	0
T100	0	4	0	1
T101	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	150196	0	0
T4	2004	7	0	0
T5	0	655	0	0
T6	0	612	0	0
T7	0	1160	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T15	0	652	0	0
T16	0	604	0	0
T17	0	600	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T33	0	7	0	0
T45	1264	0	0	0
T66	0	452	0	0
T82	1181	0	0	0
T85	1478	0	0	0
T87	0	1134	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	577130	0	292
T1	2219	133	0	0
T2	3527	1112	0	2
T3	1965	504	0	0
T4	2004	1054	0	0
T10	2346	133	0	0
T11	2329	60	0	0
T14	2456	1510	0	2
T24	2003	46	0	0
T25	1460	1360	0	2
T26	1521	1463	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2
T84	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	2564	0	83
T11	2329	0	0	0
T14	2456	4	0	0
T26	1521	0	0	0
T29	2351	0	0	0
T30	2211	42	0	1
T31	2857	0	0	0
T43	0	17	0	1
T44	0	4	0	1
T45	1264	0	0	0
T47	0	3	0	1
T53	0	0	0	1
T57	0	1	0	0
T74	0	0	0	1
T82	1181	0	0	0
T83	734	0	0	0
T85	1478	0	0	0
T97	0	3	0	1
T102	0	3	0	1
T103	0	3	0	1
T104	0	4	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	150196	0	0
T4	2004	7	0	0
T5	0	655	0	0
T6	0	612	0	0
T7	0	1160	0	0
T10	2346	0	0	0
T11	2329	0	0	0
T14	2456	0	0	0
T15	0	652	0	0
T16	0	604	0	0
T17	0	600	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T33	0	7	0	0
T45	1264	0	0	0
T66	0	452	0	0
T82	1181	0	0	0
T85	1478	0	0	0
T87	0	1134	0	0