Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12108530	416568	0	0
boot_gen_cmd_rd_A	12108530	2704	0	0
boot_ins_cmd_rd_A	12108530	3345	0	0
ctrl_rd_A	12108530	3250	0	0
err_code_test_rd_A	12108530	2954	0	0
intr_enable_rd_A	12108530	5804	0	0
max_num_reqs_between_reseeds_rd_A	12108530	3002	0	0
regwen_rd_A	12108530	3519	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	416568	0	0
T16	1093	0	0	0
T38	223555	10967	0	0
T39	439611	25714	0	0
T40	0	7197	0	0
T65	5112	0	0	0
T66	942	0	0	0
T67	1342	0	0	0
T68	1637	0	0	0
T69	1864	0	0	0
T70	1065	0	0	0
T76	0	30930	0	0
T112	0	7456	0	0
T113	0	9847	0	0
T114	1450	0	0	0
T231	0	7883	0	0
T232	0	24012	0	0
T233	0	9223	0	0
T234	0	10506	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	2704	0	0
T116	2264	0	0	0
T160	2733	0	0	0
T165	620	0	0	0
T228	2184	0	0	0
T234	292717	332	0	0
T235	0	222	0	0
T236	0	271	0	0
T237	0	183	0	0
T238	0	133	0	0
T239	0	277	0	0
T240	0	203	0	0
T241	0	706	0	0
T242	0	75	0	0
T243	0	24	0	0
T244	951	0	0	0
T245	1203	0	0	0
T246	1660	0	0	0
T247	2333	0	0	0
T248	904	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	3345	0	0
T116	2264	0	0	0
T160	2733	0	0	0
T165	620	0	0	0
T228	2184	0	0	0
T234	292717	412	0	0
T235	0	279	0	0
T236	0	262	0	0
T237	0	240	0	0
T238	0	255	0	0
T239	0	397	0	0
T240	0	309	0	0
T241	0	728	0	0
T242	0	100	0	0
T243	0	31	0	0
T244	951	0	0	0
T245	1203	0	0	0
T246	1660	0	0	0
T247	2333	0	0	0
T248	904	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	3250	0	0
T5	1233	3	0	0
T6	1070	0	0	0
T15	1440	0	0	0
T43	1746	0	0	0
T47	2088	0	0	0
T52	847	0	0	0
T64	939	0	0	0
T87	0	1	0	0
T101	0	2	0	0
T102	876	0	0	0
T105	2948	0	0	0
T205	1932	0	0	0
T234	0	421	0	0
T235	0	281	0	0
T249	0	10	0	0
T250	0	1	0	0
T251	0	20	0	0
T252	0	2	0	0
T253	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	2954	0	0
T116	2264	0	0	0
T160	2733	0	0	0
T165	620	0	0	0
T228	2184	0	0	0
T234	292717	359	0	0
T235	0	269	0	0
T236	0	287	0	0
T237	0	194	0	0
T238	0	226	0	0
T239	0	330	0	0
T240	0	278	0	0
T241	0	616	0	0
T242	0	87	0	0
T243	0	9	0	0
T244	951	0	0	0
T245	1203	0	0	0
T246	1660	0	0	0
T247	2333	0	0	0
T248	904	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	5804	0	0
T27	1243	0	0	0
T53	2417	0	0	0
T60	2193	0	0	0
T98	1665	0	0	0
T113	240700	0	0	0
T234	0	597	0	0
T235	0	471	0	0
T236	0	365	0	0
T249	0	46	0	0
T251	0	44	0	0
T254	35543	111	0	0
T255	0	26	0	0
T256	0	31	0	0
T257	0	47	0	0
T258	0	111	0	0
T259	1342	0	0	0
T260	1964	0	0	0
T261	728	0	0	0
T262	1981	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	3002	0	0
T116	2264	0	0	0
T160	2733	0	0	0
T165	620	0	0	0
T228	2184	0	0	0
T234	292717	367	0	0
T235	0	223	0	0
T236	0	265	0	0
T237	0	214	0	0
T238	0	137	0	0
T239	0	234	0	0
T240	0	213	0	0
T241	0	657	0	0
T242	0	65	0	0
T244	951	0	0	0
T245	1203	0	0	0
T246	1660	0	0	0
T247	2333	0	0	0
T248	904	0	0	0
T263	0	35	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12108530	3519	0	0
T116	2264	0	0	0
T160	2733	0	0	0
T165	620	0	0	0
T228	2184	0	0	0
T234	292717	404	0	0
T235	0	332	0	0
T236	0	281	0	0
T237	0	230	0	0
T238	0	219	0	0
T239	0	424	0	0
T240	0	276	0	0
T241	0	685	0	0
T242	0	88	0	0
T244	951	0	0	0
T245	1203	0	0	0
T246	1660	0	0	0
T247	2333	0	0	0
T248	904	0	0	0
T263	0	24	0	0