Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.25	93.91	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.02	99.92	92.66	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T24,T25,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T6,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T24	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T24	Yes	T1,T2,T24	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T41,T42	Yes	T4,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T24,T25,T4	Yes	T2,T24,T25	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T26,T9,T43	Yes	T26,T9,T43	INPUT
edn_i[2].edn_req	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
edn_i[3].edn_req	Yes	Yes	T29,T43,T46	Yes	T29,T43,T46	INPUT
edn_i[4].edn_req	Yes	Yes	T43,T47,T48	Yes	T43,T47,T48	INPUT
edn_i[5].edn_req	Yes	Yes	T26,T44,T6	Yes	T26,T44,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T25,T43,T5	Yes	T25,T43,T5	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T26,T9,T43	Yes	T26,T9,T43	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T21,T47,T49	Yes	T9,T43,T21	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T26,T9,T43	Yes	T26,T9,T43	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T45,T46,T50	Yes	T45,T46,T50	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T45,T46,T50	Yes	T45,T46,T50	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T29,T43,T46	Yes	T29,T43,T46	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T43,T46,T51	Yes	T43,T46,T17	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T29,T43,T46	Yes	T29,T43,T46	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T43,T47,T48	Yes	T43,T47,T48	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T43,T47,T52	Yes	T43,T47,T48	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T43,T47,T48	Yes	T43,T47,T48	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T26,T44,T53	Yes	T26,T44,T53	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T26,T44,T54	Yes	T26,T44,T53	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T26,T44,T53	Yes	T26,T44,T53	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T25,T43,T5	Yes	T25,T43,T5	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T23,T55,T56	Yes	T57,T58,T59	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T25,T43,T5	Yes	T25,T43,T5	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T27,T45,T60	Yes	T27,T45,T60	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T28,T61,T62	Yes	T28,T61,T62	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T28,T61,T62	Yes	T28,T61,T62	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T4,T41	Yes	T3,T4,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	12230911	12067985	0	0
CsrngAppIfOut_A	12230911	12067985	0	0
FpvSecCmCntAlertCheck_A	12230911	107	0	0
FpvSecCmGenCmdFifoRptrCheck_A	12230911	60	0	0
FpvSecCmGenCmdFifoWptrCheck_A	12230911	60	0	0
FpvSecCmMainFsmCheck_A	12230911	60	0	0
FpvSecCmRegWeOnehotCheck_A	12230911	60	0	0
FpvSecCmResCmdFifoRptrCheck_A	12230911	60	0	0
FpvSecCmResCmdFifoWptrCheck_A	12230911	60	0	0
IntrEdnCmdReqDoneKnownO_A	12230911	12067985	0	0
TlAReadyKnownO_A	12230911	12067985	0	0
TlDValidKnownO_A	12230911	12067985	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	12230911	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	12230911	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	12230911	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	12230911	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	12230911	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	12230911	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	12230911	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	12230911	500796	0	284
gen_edn_if_asserts[0].EdnDataStable_A	12230911	74067	0	446
gen_edn_if_asserts[0].EdnEndPointOut_A	12230911	12067985	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	12230911	137708	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	12230911	500796	0	284
gen_edn_if_asserts[1].EdnDataStable_A	12230911	55039	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	12230911	12067985	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	12230911	137708	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	12230911	500796	0	284
gen_edn_if_asserts[2].EdnDataStable_A	12230911	6700	0	139
gen_edn_if_asserts[2].EdnEndPointOut_A	12230911	12067985	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	12230911	137708	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	12230911	500796	0	284
gen_edn_if_asserts[3].EdnDataStable_A	12230911	4635	0	108
gen_edn_if_asserts[3].EdnEndPointOut_A	12230911	12067985	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	12230911	137708	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	12230911	500796	0	284
gen_edn_if_asserts[4].EdnDataStable_A	12230911	2481	0	109
gen_edn_if_asserts[4].EdnEndPointOut_A	12230911	12067985	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	12230911	137708	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	12230911	500796	0	284
gen_edn_if_asserts[5].EdnDataStable_A	12230911	3205	0	89
gen_edn_if_asserts[5].EdnEndPointOut_A	12230911	12067985	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	12230911	137708	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	12230911	500796	0	284
gen_edn_if_asserts[6].EdnDataStable_A	12230911	2083	0	73
gen_edn_if_asserts[6].EdnEndPointOut_A	12230911	12067985	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	12230911	137708	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	107	0	0
T5	2083	1	0	0
T8	0	1	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	1	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	60	0	0
T18	21896	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T56	1922	0	0	0
T70	0	10	0	0
T71	0	10	0	0
T72	3022	0	0	0
T73	2212	0	0	0
T74	3084	0	0	0
T75	4212	0	0	0
T76	1428	0	0	0
T77	7695	0	0	0
T78	1625	0	0	0
T79	17730	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	500796	0	284
T1	2139	12	0	0
T2	3555	26	0	0
T3	11991	3612	0	0
T4	157798	1025	0	2
T24	1962	226	0	0
T25	1670	133	0	0
T26	2304	143	0	0
T27	2018	182	0	0
T28	745	657	0	2
T29	1263	62	0	0
T41	0	0	0	2
T42	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	74067	0	446
T1	2139	26	0	1
T2	3555	9	0	1
T3	11991	16	0	0
T4	157798	23	0	0
T10	0	0	0	1
T24	1962	8	0	1
T25	1670	0	0	0
T26	2304	0	0	0
T27	2018	4	0	1
T28	745	0	0	0
T29	1263	0	0	0
T45	0	4	0	1
T60	0	0	0	1
T84	0	27	0	1
T85	0	3	0	1
T86	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	137708	0	0
T5	2083	1085	0	0
T6	0	1139	0	0
T7	0	1110	0	0
T8	0	354	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	478	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T33	0	7	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1090	0	0
T63	0	344	0	0
T87	0	602	0	0
T88	0	262	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	500796	0	284
T1	2139	12	0	0
T2	3555	26	0	0
T3	11991	3612	0	0
T4	157798	1025	0	2
T24	1962	226	0	0
T25	1670	133	0	0
T26	2304	143	0	0
T27	2018	182	0	0
T28	745	657	0	2
T29	1263	62	0	0
T41	0	0	0	2
T42	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	55039	0	132
T4	157798	0	0	0
T9	2921	4	0	1
T21	0	128	0	1
T26	2304	4	0	1
T27	2018	0	0	0
T28	745	0	0	0
T29	1263	0	0	0
T43	0	3	0	1
T44	2467	0	0	0
T47	0	52	0	1
T49	0	10	0	1
T52	0	19	0	1
T61	722	0	0	0
T84	2436	0	0	0
T85	1344	0	0	0
T89	0	3	0	1
T90	0	3	0	1
T91	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	137708	0	0
T5	2083	1085	0	0
T6	0	1139	0	0
T7	0	1110	0	0
T8	0	354	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	478	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T33	0	7	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1090	0	0
T63	0	344	0	0
T87	0	602	0	0
T88	0	262	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	500796	0	284
T1	2139	12	0	0
T2	3555	26	0	0
T3	11991	3612	0	0
T4	157798	1025	0	2
T24	1962	226	0	0
T25	1670	133	0	0
T26	2304	143	0	0
T27	2018	182	0	0
T28	745	657	0	2
T29	1263	62	0	0
T41	0	0	0	2
T42	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	6700	0	139
T9	2921	0	0	0
T43	1749	0	0	0
T44	2467	4	0	1
T45	1823	4	0	0
T46	3479	22	0	1
T47	0	57	0	1
T48	0	3	0	1
T50	0	58	0	1
T52	0	3	0	1
T60	1905	0	0	0
T61	722	0	0	0
T62	959	0	0	0
T80	880	0	0	0
T82	0	4	0	0
T86	4003	0	0	0
T90	0	0	0	1
T91	0	0	0	1
T92	0	4	0	1
T93	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	137708	0	0
T5	2083	1085	0	0
T6	0	1139	0	0
T7	0	1110	0	0
T8	0	354	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	478	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T33	0	7	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1090	0	0
T63	0	344	0	0
T87	0	602	0	0
T88	0	262	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	500796	0	284
T1	2139	12	0	0
T2	3555	26	0	0
T3	11991	3612	0	0
T4	157798	1025	0	2
T24	1962	226	0	0
T25	1670	133	0	0
T26	2304	143	0	0
T27	2018	182	0	0
T28	745	657	0	2
T29	1263	62	0	0
T41	0	0	0	2
T42	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	4635	0	108
T9	2921	0	0	0
T17	0	4	0	1
T29	1263	4	0	0
T43	1749	20	0	1
T44	2467	0	0	0
T45	1823	0	0	0
T46	0	61	0	1
T49	0	10	0	1
T51	0	61	0	1
T57	0	0	0	1
T61	722	0	0	0
T62	959	0	0	0
T84	2436	0	0	0
T85	1344	0	0	0
T86	4003	0	0	0
T91	0	38	0	1
T94	0	4	0	0
T95	0	3	0	1
T96	0	3	0	1
T97	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	137708	0	0
T5	2083	1085	0	0
T6	0	1139	0	0
T7	0	1110	0	0
T8	0	354	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	478	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T33	0	7	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1090	0	0
T63	0	344	0	0
T87	0	602	0	0
T88	0	262	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	500796	0	284
T1	2139	12	0	0
T2	3555	26	0	0
T3	11991	3612	0	0
T4	157798	1025	0	2
T24	1962	226	0	0
T25	1670	133	0	0
T26	2304	143	0	0
T27	2018	182	0	0
T28	745	657	0	2
T29	1263	62	0	0
T41	0	0	0	2
T42	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	2481	0	109
T5	2083	0	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T43	1749	47	0	1
T45	1823	0	0	0
T46	3479	0	0	0
T47	0	10	0	1
T48	0	3	0	1
T49	0	22	0	1
T51	0	15	0	1
T52	0	29	0	1
T60	1905	0	0	0
T62	959	0	0	0
T80	880	0	0	0
T82	0	1	0	0
T90	0	3	0	1
T91	0	25	0	1
T95	0	0	0	1
T98	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	137708	0	0
T5	2083	1085	0	0
T6	0	1139	0	0
T7	0	1110	0	0
T8	0	354	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	478	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T33	0	7	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1090	0	0
T63	0	344	0	0
T87	0	602	0	0
T88	0	262	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	500796	0	284
T1	2139	12	0	0
T2	3555	26	0	0
T3	11991	3612	0	0
T4	157798	1025	0	2
T24	1962	226	0	0
T25	1670	133	0	0
T26	2304	143	0	0
T27	2018	182	0	0
T28	745	657	0	2
T29	1263	62	0	0
T41	0	0	0	2
T42	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	3205	0	89
T4	157798	0	0	0
T9	2921	0	0	0
T23	0	0	0	1
T26	2304	4	0	0
T27	2018	0	0	0
T28	745	0	0	0
T29	1263	0	0	0
T44	2467	4	0	0
T49	0	15	0	1
T52	0	3	0	1
T53	0	4	0	1
T54	0	1	0	0
T57	0	59	0	1
T61	722	0	0	0
T84	2436	0	0	0
T85	1344	0	0	0
T91	0	3	0	1
T92	0	4	0	0
T99	0	4	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	137708	0	0
T5	2083	1085	0	0
T6	0	1139	0	0
T7	0	1110	0	0
T8	0	354	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	478	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T33	0	7	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1090	0	0
T63	0	344	0	0
T87	0	602	0	0
T88	0	262	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	500796	0	284
T1	2139	12	0	0
T2	3555	26	0	0
T3	11991	3612	0	0
T4	157798	1025	0	2
T24	1962	226	0	0
T25	1670	133	0	0
T26	2304	143	0	0
T27	2018	182	0	0
T28	745	657	0	2
T29	1263	62	0	0
T41	0	0	0	2
T42	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	2083	0	73
T4	157798	0	0	0
T5	0	1	0	0
T9	2921	0	0	0
T23	0	32	0	1
T25	1670	4	0	1
T26	2304	0	0	0
T27	2018	0	0	0
T28	745	0	0	0
T29	1263	0	0	0
T43	0	3	0	1
T44	2467	0	0	0
T49	0	3	0	1
T52	0	3	0	1
T55	0	0	0	1
T57	0	3	0	1
T58	0	4	0	1
T59	0	3	0	1
T84	2436	0	0	0
T85	1344	0	0	0
T99	0	4	0	0
T101	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	137708	0	0
T5	2083	1085	0	0
T6	0	1139	0	0
T7	0	1110	0	0
T8	0	354	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	478	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T33	0	7	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1090	0	0
T63	0	344	0	0
T87	0	602	0	0
T88	0	262	0	0