Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12710607	440037	0	0
boot_gen_cmd_rd_A	12710607	2420	0	0
boot_ins_cmd_rd_A	12710607	2853	0	0
ctrl_rd_A	12710607	2406	0	0
err_code_test_rd_A	12710607	2838	0	0
intr_enable_rd_A	12710607	5401	0	0
max_num_reqs_between_reseeds_rd_A	12710607	2911	0	0
regwen_rd_A	12710607	3139	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	440037	0	0
T4	157798	9362	0	0
T9	2921	0	0	0
T27	2018	0	0	0
T28	745	0	0	0
T29	1263	0	0	0
T41	0	11053	0	0
T42	0	10890	0	0
T44	2467	0	0	0
T61	722	0	0	0
T81	0	20838	0	0
T83	0	18808	0	0
T84	2436	0	0	0
T85	1344	0	0	0
T86	4003	0	0	0
T114	0	12642	0	0
T199	0	12954	0	0
T220	0	19340	0	0
T221	0	8600	0	0
T222	0	9592	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	2420	0	0
T23	7100	0	0	0
T55	2742	0	0	0
T97	2285	0	0	0
T100	2379	0	0	0
T107	1236	0	0	0
T134	2510	0	0	0
T200	884	0	0	0
T220	501722	598	0	0
T221	0	177	0	0
T223	0	168	0	0
T224	0	293	0	0
T225	0	186	0	0
T226	0	97	0	0
T227	0	213	0	0
T228	0	325	0	0
T229	0	7	0	0
T230	0	4	0	0
T231	881	0	0	0
T232	2050	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	2853	0	0
T23	7100	0	0	0
T55	2742	0	0	0
T97	2285	0	0	0
T100	2379	0	0	0
T107	1236	0	0	0
T134	2510	0	0	0
T200	884	0	0	0
T220	501722	665	0	0
T221	0	175	0	0
T223	0	164	0	0
T224	0	394	0	0
T225	0	271	0	0
T226	0	95	0	0
T227	0	232	0	0
T228	0	462	0	0
T229	0	7	0	0
T231	881	0	0	0
T232	2050	0	0	0
T233	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	2406	0	0
T5	2083	0	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T60	1905	6	0	0
T204	0	6	0	0
T220	0	542	0	0
T221	0	131	0	0
T223	0	193	0	0
T224	0	221	0	0
T225	0	221	0	0
T234	0	13	0	0
T235	0	4	0	0
T236	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	2838	0	0
T23	7100	0	0	0
T55	2742	0	0	0
T97	2285	0	0	0
T100	2379	0	0	0
T107	1236	0	0	0
T134	2510	0	0	0
T200	884	0	0	0
T220	501722	684	0	0
T221	0	162	0	0
T223	0	278	0	0
T224	0	330	0	0
T225	0	313	0	0
T226	0	60	0	0
T227	0	187	0	0
T228	0	403	0	0
T229	0	7	0	0
T230	0	4	0	0
T231	881	0	0	0
T232	2050	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	5401	0	0
T23	7100	0	0	0
T55	2742	0	0	0
T79	0	58	0	0
T97	2285	0	0	0
T100	2379	0	0	0
T107	1236	0	0	0
T134	2510	0	0	0
T200	884	0	0	0
T220	501722	991	0	0
T221	0	353	0	0
T223	0	292	0	0
T231	881	0	0	0
T232	2050	0	0	0
T234	0	27	0	0
T237	0	15	0	0
T238	0	86	0	0
T239	0	10	0	0
T240	0	20	0	0
T241	0	26	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	2911	0	0
T23	7100	0	0	0
T55	2742	0	0	0
T97	2285	0	0	0
T100	2379	0	0	0
T107	1236	0	0	0
T134	2510	0	0	0
T200	884	0	0	0
T220	501722	594	0	0
T221	0	181	0	0
T223	0	200	0	0
T224	0	231	0	0
T225	0	227	0	0
T226	0	60	0	0
T227	0	167	0	0
T228	0	418	0	0
T229	0	7	0	0
T230	0	5	0	0
T231	881	0	0	0
T232	2050	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12710607	3139	0	0
T23	7100	0	0	0
T55	2742	0	0	0
T97	2285	0	0	0
T100	2379	0	0	0
T107	1236	0	0	0
T134	2510	0	0	0
T200	884	0	0	0
T220	501722	692	0	0
T221	0	183	0	0
T223	0	207	0	0
T224	0	200	0	0
T225	0	272	0	0
T226	0	110	0	0
T227	0	208	0	0
T228	0	378	0	0
T229	0	12	0	0
T230	0	1	0	0
T231	881	0	0	0
T232	2050	0	0	0