Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	98.25	93.97	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.23	99.92	92.75	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T10,T34

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T4,T39,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T28,T29	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T27,T10	Yes	T3,T27,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T26	Yes	T1,T3,T26	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T26,T27	Yes	T1,T3,T26	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T26	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T34,T11	Yes	T1,T34,T11	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T39,T47	Yes	T1,T39,T47	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T4,T47	Yes	T1,T4,T47	INPUT
edn_i[5].edn_req	Yes	Yes	T6,T47,T48	Yes	T6,T47,T48	INPUT
edn_i[6].edn_req	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T27	Yes	T1,T2,T26	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T29	Yes	T1,T2,T27	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T11,T50,T48	Yes	T14,T11,T47	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T34,T11	Yes	T1,T34,T11	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T50,T51	Yes	T1,T50,T52	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T34,T11	Yes	T1,T34,T11	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T47,T48	Yes	T1,T47,T48	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T51,T37,T53	Yes	T48,T51,T54	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T39,T47	Yes	T1,T39,T47	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T47,T55	Yes	T1,T47,T55	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T55,T56	Yes	T1,T55,T20	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T4,T47	Yes	T1,T4,T47	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T47,T48,T23	Yes	T47,T48,T23	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T47,T23,T57	Yes	T47,T48,T23	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T47,T48,T23	Yes	T47,T48,T23	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T47,T49,T25	Yes	T47,T48,T49	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T47,T25,T58	Yes	T47,T25,T58	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T27	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T29,T5	Yes	T1,T27,T29	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T29	Yes	T1,T2,T27	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T9,T34,T59	Yes	T9,T34,T59	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T10,T34	Yes	T9,T10,T34	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T39,T6	Yes	T4,T39,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T10,T34	Yes	T9,T10,T34	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T39,T6	Yes	T4,T39,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T2,T5,T30	Yes	T2,T5,T30	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	12074411	11898612	0	0
CsrngAppIfOut_A	12074411	11898612	0	0
FpvSecCmCntAlertCheck_A	12074411	109	0	0
FpvSecCmGenCmdFifoRptrCheck_A	12074411	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	12074411	70	0	0
FpvSecCmMainFsmCheck_A	12074411	70	0	0
FpvSecCmRegWeOnehotCheck_A	12074411	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	12074411	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	12074411	70	0	0
IntrEdnCmdReqDoneKnownO_A	12074411	11898612	0	0
TlAReadyKnownO_A	12074411	11898612	0	0
TlDValidKnownO_A	12074411	11898612	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	12074411	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	12074411	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	12074411	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	12074411	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	12074411	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	12074411	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	12074411	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	12074411	545554	0	306
gen_edn_if_asserts[0].EdnDataStable_A	12074411	122633	0	424
gen_edn_if_asserts[0].EdnEndPointOut_A	12074411	11898612	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	12074411	136756	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	12074411	545554	0	306
gen_edn_if_asserts[1].EdnDataStable_A	12074411	54769	0	118
gen_edn_if_asserts[1].EdnEndPointOut_A	12074411	11898612	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	12074411	136756	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	12074411	545554	0	306
gen_edn_if_asserts[2].EdnDataStable_A	12074411	4050	0	120
gen_edn_if_asserts[2].EdnEndPointOut_A	12074411	11898612	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	12074411	136756	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	12074411	545554	0	306
gen_edn_if_asserts[3].EdnDataStable_A	12074411	2839	0	110
gen_edn_if_asserts[3].EdnEndPointOut_A	12074411	11898612	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	12074411	136756	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	12074411	545554	0	306
gen_edn_if_asserts[4].EdnDataStable_A	12074411	52284	0	87
gen_edn_if_asserts[4].EdnEndPointOut_A	12074411	11898612	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	12074411	136756	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	12074411	545554	0	306
gen_edn_if_asserts[5].EdnDataStable_A	12074411	4290	0	89
gen_edn_if_asserts[5].EdnEndPointOut_A	12074411	11898612	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	12074411	136756	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	12074411	545554	0	306
gen_edn_if_asserts[6].EdnDataStable_A	12074411	1314	0	75
gen_edn_if_asserts[6].EdnEndPointOut_A	12074411	11898612	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	12074411	136756	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	109	0	0
T8	1351	1	0	0
T15	560	1	0	0
T16	1289	1	0	0
T17	0	10	0	0
T37	1946	0	0	0
T56	1211	1	0	0
T60	2443	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	1556	0	0	0
T66	1874	0	0	0
T67	2782	0	0	0
T68	2014	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	70	0	0
T17	24455	10	0	0
T18	0	10	0	0
T19	0	20	0	0
T53	2678	0	0	0
T62	823	0	0	0
T69	0	20	0	0
T70	0	10	0	0
T71	1172	0	0	0
T72	7233	0	0	0
T73	16808	0	0	0
T74	2353	0	0	0
T75	2258	0	0	0
T76	1758	0	0	0
T77	2538	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	545554	0	306
T1	4721	16	0	0
T2	17464	2335	0	0
T3	921	31	0	0
T4	2014	996	0	0
T5	34029	2751	0	0
T20	0	0	0	2
T21	0	0	0	2
T26	1301	11	0	0
T27	2677	19	0	0
T28	2666	91	0	0
T29	2685	22	0	0
T30	32026	1104	0	0
T44	0	0	0	2
T67	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	122633	0	424
T1	4721	17	0	1
T2	17464	15	0	0
T3	921	0	0	0
T4	2014	0	0	0
T5	34029	15	0	0
T10	0	4	0	1
T11	0	0	0	1
T26	1301	3	0	1
T27	2677	19	0	1
T28	2666	3	0	1
T29	2685	32	0	1
T30	32026	41	0	1
T44	0	73	0	0
T59	0	0	0	1
T84	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	136756	0	0
T4	2014	1070	0	0
T5	34029	0	0	0
T6	1075	345	0	0
T7	0	622	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	210	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	7	0	0
T39	1193	497	0	0
T44	204185	0	0	0
T85	0	170	0	0
T86	0	637	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	545554	0	306
T1	4721	16	0	0
T2	17464	2335	0	0
T3	921	31	0	0
T4	2014	996	0	0
T5	34029	2751	0	0
T20	0	0	0	2
T21	0	0	0	2
T26	1301	11	0	0
T27	2677	19	0	0
T28	2666	91	0	0
T29	2685	22	0	0
T30	32026	1104	0	0
T44	0	0	0	2
T67	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	54769	0	118
T1	4721	19	0	1
T2	17464	0	0	0
T3	921	3	0	1
T4	2014	0	0	0
T5	34029	0	0	0
T9	0	4	0	1
T11	0	9	0	1
T14	0	4	0	1
T26	1301	0	0	0
T27	2677	0	0	0
T28	2666	0	0	0
T29	2685	0	0	0
T30	32026	0	0	0
T47	0	3	0	1
T50	0	25	0	1
T87	0	3	0	1
T88	0	4	0	1
T89	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	136756	0	0
T4	2014	1070	0	0
T5	34029	0	0	0
T6	1075	345	0	0
T7	0	622	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	210	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	7	0	0
T39	1193	497	0	0
T44	204185	0	0	0
T85	0	170	0	0
T86	0	637	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	545554	0	306
T1	4721	16	0	0
T2	17464	2335	0	0
T3	921	31	0	0
T4	2014	996	0	0
T5	34029	2751	0	0
T20	0	0	0	2
T21	0	0	0	2
T26	1301	11	0	0
T27	2677	19	0	0
T28	2666	91	0	0
T29	2685	22	0	0
T30	32026	1104	0	0
T44	0	0	0	2
T67	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	4050	0	120
T1	4721	32	0	1
T2	17464	0	0	0
T3	921	0	0	0
T4	2014	0	0	0
T5	34029	0	0	0
T11	0	10	0	1
T26	1301	0	0	0
T27	2677	0	0	0
T28	2666	0	0	0
T29	2685	0	0	0
T30	32026	0	0	0
T34	0	4	0	1
T47	0	3	0	1
T48	0	3	0	1
T50	0	49	0	1
T51	0	20	0	1
T52	0	4	0	1
T90	0	3	0	1
T91	0	4	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	136756	0	0
T4	2014	1070	0	0
T5	34029	0	0	0
T6	1075	345	0	0
T7	0	622	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	210	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	7	0	0
T39	1193	497	0	0
T44	204185	0	0	0
T85	0	170	0	0
T86	0	637	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	545554	0	306
T1	4721	16	0	0
T2	17464	2335	0	0
T3	921	31	0	0
T4	2014	996	0	0
T5	34029	2751	0	0
T20	0	0	0	2
T21	0	0	0	2
T26	1301	11	0	0
T27	2677	19	0	0
T28	2666	91	0	0
T29	2685	22	0	0
T30	32026	1104	0	0
T44	0	0	0	2
T67	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	2839	0	110
T1	4721	3	0	1
T2	17464	0	0	0
T3	921	0	0	0
T4	2014	0	0	0
T5	34029	0	0	0
T22	0	3	0	1
T26	1301	0	0	0
T27	2677	0	0	0
T28	2666	0	0	0
T29	2685	0	0	0
T30	32026	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	0	3	0	1
T48	0	16	0	1
T51	0	40	0	1
T53	0	0	0	1
T54	0	11	0	1
T57	0	3	0	1
T75	0	0	0	1
T92	0	4	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	136756	0	0
T4	2014	1070	0	0
T5	34029	0	0	0
T6	1075	345	0	0
T7	0	622	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	210	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	7	0	0
T39	1193	497	0	0
T44	204185	0	0	0
T85	0	170	0	0
T86	0	637	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	545554	0	306
T1	4721	16	0	0
T2	17464	2335	0	0
T3	921	31	0	0
T4	2014	996	0	0
T5	34029	2751	0	0
T20	0	0	0	2
T21	0	0	0	2
T26	1301	11	0	0
T27	2677	19	0	0
T28	2666	91	0	0
T29	2685	22	0	0
T30	32026	1104	0	0
T44	0	0	0	2
T67	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	52284	0	87
T1	4721	37	0	1
T2	17464	0	0	0
T3	921	0	0	0
T4	2014	1	0	0
T5	34029	0	0	0
T12	0	0	0	1
T13	0	0	0	1
T20	0	4	0	0
T22	0	31	0	1
T26	1301	0	0	0
T27	2677	0	0	0
T28	2666	0	0	0
T29	2685	0	0	0
T30	32026	0	0	0
T47	0	9	0	1
T51	0	3	0	1
T55	0	4	0	0
T56	0	1	0	0
T93	0	4	0	0
T94	0	3	0	1
T95	0	0	0	1
T96	0	0	0	1
T97	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	136756	0	0
T4	2014	1070	0	0
T5	34029	0	0	0
T6	1075	345	0	0
T7	0	622	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	210	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	7	0	0
T39	1193	497	0	0
T44	204185	0	0	0
T85	0	170	0	0
T86	0	637	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	545554	0	306
T1	4721	16	0	0
T2	17464	2335	0	0
T3	921	31	0	0
T4	2014	996	0	0
T5	34029	2751	0	0
T20	0	0	0	2
T21	0	0	0	2
T26	1301	11	0	0
T27	2677	19	0	0
T28	2666	91	0	0
T29	2685	22	0	0
T30	32026	1104	0	0
T44	0	0	0	2
T67	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	4290	0	89
T12	0	3	0	1
T22	0	16	0	1
T23	0	4	0	0
T25	0	18	0	1
T47	3596	50	0	1
T48	3368	3	0	1
T50	3742	0	0	0
T52	2355	0	0	0
T53	0	10	0	1
T55	914	0	0	0
T57	0	16	0	1
T88	2699	0	0	0
T89	2041	0	0	0
T93	849	0	0	0
T98	0	3	0	1
T99	0	4	0	1
T100	23509	0	0	0
T101	1931	0	0	0
T102	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	136756	0	0
T4	2014	1070	0	0
T5	34029	0	0	0
T6	1075	345	0	0
T7	0	622	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	210	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	7	0	0
T39	1193	497	0	0
T44	204185	0	0	0
T85	0	170	0	0
T86	0	637	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	545554	0	306
T1	4721	16	0	0
T2	17464	2335	0	0
T3	921	31	0	0
T4	2014	996	0	0
T5	34029	2751	0	0
T20	0	0	0	2
T21	0	0	0	2
T26	1301	11	0	0
T27	2677	19	0	0
T28	2666	91	0	0
T29	2685	22	0	0
T30	32026	1104	0	0
T44	0	0	0	2
T67	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2
T83	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	1314	0	75
T12	0	43	0	1
T13	0	0	0	1
T25	0	48	0	1
T47	3596	20	0	1
T48	3368	3	0	1
T49	0	4	0	1
T50	3742	0	0	0
T52	2355	0	0	0
T55	914	0	0	0
T58	0	4	0	0
T88	2699	0	0	0
T89	2041	0	0	0
T93	849	0	0	0
T94	0	11	0	1
T96	0	0	0	1
T98	0	3	0	1
T100	23509	0	0	0
T101	1931	0	0	0
T103	0	4	0	0
T104	0	16	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	136756	0	0
T4	2014	1070	0	0
T5	34029	0	0	0
T6	1075	345	0	0
T7	0	622	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	210	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	7	0	0
T39	1193	497	0	0
T44	204185	0	0	0
T85	0	170	0	0
T86	0	637	0	0