Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12594847	409686	0	0
boot_gen_cmd_rd_A	12594847	2842	0	0
boot_ins_cmd_rd_A	12594847	3540	0	0
ctrl_rd_A	12594847	3422	0	0
err_code_test_rd_A	12594847	3320	0	0
intr_enable_rd_A	12594847	8040	0	0
max_num_reqs_between_reseeds_rd_A	12594847	4152	0	0
regwen_rd_A	12594847	4793	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	409686	0	0
T11	3106	0	0	0
T14	1625	0	0	0
T44	204185	9305	0	0
T45	0	3632	0	0
T46	0	6550	0	0
T47	3596	0	0	0
T50	3742	0	0	0
T52	2355	0	0	0
T59	1713	0	0	0
T84	1793	0	0	0
T87	839	0	0	0
T88	2699	0	0	0
T233	0	8766	0	0
T234	0	5879	0	0
T235	0	11248	0	0
T236	0	17988	0	0
T237	0	24560	0	0
T238	0	11135	0	0
T239	0	10721	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	2842	0	0
T12	4505	0	0	0
T46	173263	93	0	0
T107	2564	0	0	0
T184	2313	0	0	0
T203	2016	0	0	0
T233	0	111	0	0
T239	0	379	0	0
T240	0	468	0	0
T241	0	330	0	0
T242	0	317	0	0
T243	0	275	0	0
T244	0	165	0	0
T245	0	414	0	0
T246	0	28	0	0
T247	3327	0	0	0
T248	1872	0	0	0
T249	1525	0	0	0
T250	1900	0	0	0
T251	1882	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	3540	0	0
T12	4505	0	0	0
T46	173263	203	0	0
T107	2564	0	0	0
T184	2313	0	0	0
T203	2016	0	0	0
T233	0	157	0	0
T239	0	404	0	0
T240	0	693	0	0
T241	0	363	0	0
T242	0	371	0	0
T243	0	343	0	0
T244	0	237	0	0
T245	0	506	0	0
T247	3327	0	0	0
T248	1872	0	0	0
T249	1525	0	0	0
T250	1900	0	0	0
T251	1882	0	0	0
T252	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	3422	0	0
T4	2014	0	0	0
T5	34029	0	0	0
T6	1075	0	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T29	2685	3	0	0
T30	32026	5	0	0
T33	0	4	0	0
T34	1913	0	0	0
T39	1193	0	0	0
T44	204185	0	0	0
T46	0	170	0	0
T100	0	1	0	0
T179	0	2	0	0
T233	0	143	0	0
T239	0	323	0	0
T253	0	9	0	0
T254	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	3320	0	0
T12	4505	0	0	0
T46	173263	133	0	0
T107	2564	0	0	0
T184	2313	0	0	0
T203	2016	0	0	0
T233	0	209	0	0
T239	0	409	0	0
T240	0	488	0	0
T241	0	418	0	0
T242	0	414	0	0
T243	0	315	0	0
T244	0	183	0	0
T245	0	484	0	0
T247	3327	0	0	0
T248	1872	0	0	0
T249	1525	0	0	0
T250	1900	0	0	0
T251	1882	0	0	0
T252	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	8040	0	0
T6	1075	0	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T11	3106	0	0	0
T14	1625	0	0	0
T30	32026	44	0	0
T34	1913	0	0	0
T39	1193	0	0	0
T44	204185	0	0	0
T46	0	252	0	0
T80	0	43	0	0
T84	1793	0	0	0
T100	0	94	0	0
T233	0	360	0	0
T253	0	92	0	0
T254	0	32	0	0
T255	0	21	0	0
T256	0	54	0	0
T257	0	17	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	4152	0	0
T12	4505	0	0	0
T46	173263	139	0	0
T107	2564	0	0	0
T184	2313	0	0	0
T203	2016	0	0	0
T233	0	136	0	0
T239	0	341	0	0
T240	0	517	0	0
T241	0	385	0	0
T242	0	317	0	0
T243	0	286	0	0
T244	0	172	0	0
T245	0	386	0	0
T247	3327	0	0	0
T248	1872	0	0	0
T249	1525	0	0	0
T250	1900	0	0	0
T251	1882	0	0	0
T252	0	45	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12594847	4793	0	0
T12	4505	0	0	0
T46	173263	154	0	0
T107	2564	0	0	0
T184	2313	0	0	0
T203	2016	0	0	0
T233	0	249	0	0
T239	0	305	0	0
T240	0	624	0	0
T241	0	363	0	0
T242	0	353	0	0
T243	0	379	0	0
T244	0	254	0	0
T245	0	448	0	0
T247	3327	0	0	0
T248	1872	0	0	0
T249	1525	0	0	0
T250	1900	0	0	0
T251	1882	0	0	0
T252	0	36	0	0