Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	98.25	93.97	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.13	99.92	92.75	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T10,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T5,T33,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T4,T38	Yes	T2,T4,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
edn_i[1].edn_req	Yes	Yes	T26,T29,T30	Yes	T26,T29,T30	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T26,T30	Yes	T1,T26,T30	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T23,T26	Yes	T1,T23,T26	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T5,T30	Yes	T3,T5,T30	INPUT
edn_i[5].edn_req	Yes	Yes	T39,T40,T30	Yes	T39,T40,T30	INPUT
edn_i[6].edn_req	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T9,T23,T4	Yes	T1,T9,T23	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T26,T29,T42	Yes	T26,T29,T30	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T26,T44,T45	Yes	T26,T29,T22	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T26,T29,T30	Yes	T26,T29,T30	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T26,T30	Yes	T1,T26,T30	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T46,T45	Yes	T1,T26,T30	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T26,T30	Yes	T1,T26,T30	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T23,T26	Yes	T1,T23,T26	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T26,T6	Yes	T1,T23,T26	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T23,T26	Yes	T1,T23,T26	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T30,T47	Yes	T3,T30,T47	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T48,T49,T11	Yes	T3,T30,T48	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T30,T47	Yes	T3,T30,T47	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T39,T40,T30	Yes	T39,T40,T30	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T30,T47,T45	Yes	T40,T30,T47	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T39,T40,T30	Yes	T39,T40,T30	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T43,T46,T50	Yes	T41,T42,T43	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T23	Yes	T1,T2,T23	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T3,T23	Yes	T1,T3,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T9,T31,T29	Yes	T9,T31,T29	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T24,T10	Yes	T9,T24,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T24,T5,T33	Yes	T24,T5,T33	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T24,T10	Yes	T9,T24,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T24,T5,T33	Yes	T24,T5,T33	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T2,T4,T51	Yes	T2,T4,T51	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T4,T51	Yes	T2,T4,T51	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	10249775	10064284	0	0
CsrngAppIfOut_A	10249775	10064284	0	0
FpvSecCmCntAlertCheck_A	10249775	118	0	0
FpvSecCmGenCmdFifoRptrCheck_A	10249775	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	10249775	80	0	0
FpvSecCmMainFsmCheck_A	10249775	80	0	0
FpvSecCmRegWeOnehotCheck_A	10249775	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	10249775	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	10249775	80	0	0
IntrEdnCmdReqDoneKnownO_A	10249775	10064284	0	0
TlAReadyKnownO_A	10249775	10064284	0	0
TlDValidKnownO_A	10249775	10064284	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	10249775	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	10249775	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	10249775	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	10249775	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	10249775	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	10249775	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	10249775	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	10249775	547437	0	270
gen_edn_if_asserts[0].EdnDataStable_A	10249775	20599	0	410
gen_edn_if_asserts[0].EdnEndPointOut_A	10249775	10064284	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	10249775	159439	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	10249775	547437	0	270
gen_edn_if_asserts[1].EdnDataStable_A	10249775	5639	0	126
gen_edn_if_asserts[1].EdnEndPointOut_A	10249775	10064284	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	10249775	159439	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	10249775	547437	0	270
gen_edn_if_asserts[2].EdnDataStable_A	10249775	4657	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	10249775	10064284	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	10249775	159439	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	10249775	547437	0	270
gen_edn_if_asserts[3].EdnDataStable_A	10249775	3478	0	107
gen_edn_if_asserts[3].EdnEndPointOut_A	10249775	10064284	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	10249775	159439	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	10249775	547437	0	270
gen_edn_if_asserts[4].EdnDataStable_A	10249775	2717	0	105
gen_edn_if_asserts[4].EdnEndPointOut_A	10249775	10064284	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	10249775	159439	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	10249775	547437	0	270
gen_edn_if_asserts[5].EdnDataStable_A	10249775	2263	0	83
gen_edn_if_asserts[5].EdnEndPointOut_A	10249775	10064284	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	10249775	159439	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	10249775	547437	0	270
gen_edn_if_asserts[6].EdnDataStable_A	10249775	3570	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	10249775	10064284	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	10249775	159439	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	118	0	0
T5	671	1	0	0
T6	2417	0	0	0
T8	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	10	0	0
T16	0	20	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	2853	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	80	0	0
T15	25059	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T20	1545	0	0	0
T22	1983	0	0	0
T46	2032	0	0	0
T54	686	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	2168	0	0	0
T60	2244	0	0	0
T61	1400	0	0	0
T62	2285	0	0	0
T63	2651	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	547437	0	270
T1	5066	317	0	0
T2	130466	731	0	0
T3	2872	1574	0	2
T4	135352	786	0	2
T9	1810	132	0	0
T10	2839	445	0	0
T15	0	0	0	2
T23	2167	19	0	0
T24	1235	1151	0	2
T25	1653	18	0	0
T26	1738	11	0	0
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T61	0	0	0	2
T64	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	20599	0	410
T1	5066	3	0	1
T2	130466	37	0	1
T3	2872	0	0	0
T4	135352	45	0	0
T9	1810	8	0	1
T10	2839	4	0	1
T23	2167	22	0	1
T24	1235	0	0	0
T25	1653	3	0	1
T26	1738	3	0	1
T28	0	4	0	1
T31	0	0	0	1
T51	0	19	0	0
T56	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	159439	0	0
T5	671	335	0	0
T6	2417	1112	0	0
T13	0	1074	0	0
T14	0	594	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	24	0	0
T34	0	18	0	0
T35	0	392	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	646	0	0
T56	2853	0	0	0
T65	0	641	0	0
T66	0	1082	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	547437	0	270
T1	5066	317	0	0
T2	130466	731	0	0
T3	2872	1574	0	2
T4	135352	786	0	2
T9	1810	132	0	0
T10	2839	445	0	0
T15	0	0	0	2
T23	2167	19	0	0
T24	1235	1151	0	2
T25	1653	18	0	0
T26	1738	11	0	0
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T61	0	0	0	2
T64	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	5639	0	126
T5	671	0	0	0
T6	2417	0	0	0
T22	0	4	0	0
T26	1738	37	0	1
T28	1849	0	0	0
T29	0	4	0	1
T30	0	3	0	1
T31	1505	0	0	0
T33	2108	0	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T42	0	3	0	1
T44	0	32	0	1
T45	0	32	0	1
T51	26137	0	0	0
T56	2853	0	0	0
T59	0	4	0	1
T67	0	4	0	1
T68	0	4	0	0
T69	0	0	0	1
T70	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	159439	0	0
T5	671	335	0	0
T6	2417	1112	0	0
T13	0	1074	0	0
T14	0	594	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	24	0	0
T34	0	18	0	0
T35	0	392	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	646	0	0
T56	2853	0	0	0
T65	0	641	0	0
T66	0	1082	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	547437	0	270
T1	5066	317	0	0
T2	130466	731	0	0
T3	2872	1574	0	2
T4	135352	786	0	2
T9	1810	132	0	0
T10	2839	445	0	0
T15	0	0	0	2
T23	2167	19	0	0
T24	1235	1151	0	2
T25	1653	18	0	0
T26	1738	11	0	0
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T61	0	0	0	2
T64	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	4657	0	127
T1	5066	62	0	1
T2	130466	0	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	4	0	1
T30	0	3	0	1
T42	0	3	0	1
T44	0	3	0	1
T46	0	12	0	1
T48	0	26	0	1
T71	0	4	0	1
T72	0	3	0	1
T73	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	159439	0	0
T5	671	335	0	0
T6	2417	1112	0	0
T13	0	1074	0	0
T14	0	594	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	24	0	0
T34	0	18	0	0
T35	0	392	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	646	0	0
T56	2853	0	0	0
T65	0	641	0	0
T66	0	1082	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	547437	0	270
T1	5066	317	0	0
T2	130466	731	0	0
T3	2872	1574	0	2
T4	135352	786	0	2
T9	1810	132	0	0
T10	2839	445	0	0
T15	0	0	0	2
T23	2167	19	0	0
T24	1235	1151	0	2
T25	1653	18	0	0
T26	1738	11	0	0
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T61	0	0	0	2
T64	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	3478	0	107
T1	5066	15	0	1
T2	130466	0	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T6	0	1	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	3	0	1
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	52	0	1
T30	0	21	0	1
T43	0	78	0	1
T46	0	25	0	1
T48	0	3	0	1
T62	0	4	0	1
T73	0	19	0	1
T74	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	159439	0	0
T5	671	335	0	0
T6	2417	1112	0	0
T13	0	1074	0	0
T14	0	594	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	24	0	0
T34	0	18	0	0
T35	0	392	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	646	0	0
T56	2853	0	0	0
T65	0	641	0	0
T66	0	1082	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	547437	0	270
T1	5066	317	0	0
T2	130466	731	0	0
T3	2872	1574	0	2
T4	135352	786	0	2
T9	1810	132	0	0
T10	2839	445	0	0
T15	0	0	0	2
T23	2167	19	0	0
T24	1235	1151	0	2
T25	1653	18	0	0
T26	1738	11	0	0
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T61	0	0	0	2
T64	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	2717	0	105
T3	2872	4	0	0
T4	135352	0	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T11	0	0	0	1
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T30	0	3	0	1
T45	0	3	0	1
T46	0	3	0	1
T47	0	13	0	1
T48	0	49	0	1
T49	0	1093	0	1
T51	26137	0	0	0
T69	0	3	0	1
T75	0	3	0	1
T76	0	4	0	0
T77	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	159439	0	0
T5	671	335	0	0
T6	2417	1112	0	0
T13	0	1074	0	0
T14	0	594	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	24	0	0
T34	0	18	0	0
T35	0	392	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	646	0	0
T56	2853	0	0	0
T65	0	641	0	0
T66	0	1082	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	547437	0	270
T1	5066	317	0	0
T2	130466	731	0	0
T3	2872	1574	0	2
T4	135352	786	0	2
T9	1810	132	0	0
T10	2839	445	0	0
T15	0	0	0	2
T23	2167	19	0	0
T24	1235	1151	0	2
T25	1653	18	0	0
T26	1738	11	0	0
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T61	0	0	0	2
T64	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	2263	0	83
T6	2417	0	0	0
T13	1795	0	0	0
T20	0	4	0	0
T29	1703	0	0	0
T30	2428	12	0	1
T31	1505	0	0	0
T35	974	0	0	0
T39	2492	4	0	0
T40	2842	4	0	0
T41	790	0	0	0
T43	0	3	0	1
T45	0	37	0	1
T46	0	3	0	1
T47	0	49	0	1
T69	0	0	0	1
T74	0	3	0	1
T75	0	0	0	1
T78	0	3	0	1
T79	1610	0	0	0
T80	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	159439	0	0
T5	671	335	0	0
T6	2417	1112	0	0
T13	0	1074	0	0
T14	0	594	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	24	0	0
T34	0	18	0	0
T35	0	392	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	646	0	0
T56	2853	0	0	0
T65	0	641	0	0
T66	0	1082	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	547437	0	270
T1	5066	317	0	0
T2	130466	731	0	0
T3	2872	1574	0	2
T4	135352	786	0	2
T9	1810	132	0	0
T10	2839	445	0	0
T15	0	0	0	2
T23	2167	19	0	0
T24	1235	1151	0	2
T25	1653	18	0	0
T26	1738	11	0	0
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T61	0	0	0	2
T64	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	3570	0	79
T13	1795	0	0	0
T18	5440	0	0	0
T34	621	0	0	0
T35	974	0	0	0
T41	790	3	0	1
T42	0	10	0	1
T43	0	23	0	1
T45	0	25	0	1
T46	0	15	0	1
T50	0	351	0	1
T69	0	3	0	1
T70	0	3	0	1
T74	0	3	0	1
T79	1610	0	0	0
T81	0	11	0	1
T82	1615	0	0	0
T83	896	0	0	0
T84	1991	0	0	0
T85	2638	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	159439	0	0
T5	671	335	0	0
T6	2417	1112	0	0
T13	0	1074	0	0
T14	0	594	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	24	0	0
T34	0	18	0	0
T35	0	392	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	646	0	0
T56	2853	0	0	0
T65	0	641	0	0
T66	0	1082	0	0