Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	10749503	358400	0	0
boot_gen_cmd_rd_A	10749503	2806	0	0
boot_ins_cmd_rd_A	10749503	3044	0	0
ctrl_rd_A	10749503	2701	0	0
err_code_test_rd_A	10749503	3185	0	0
intr_enable_rd_A	10749503	6083	0	0
max_num_reqs_between_reseeds_rd_A	10749503	3042	0	0
regwen_rd_A	10749503	3370	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	358400	0	0
T2	130466	4421	0	0
T3	2872	0	0	0
T4	135352	8279	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T38	0	4618	0	0
T95	0	14401	0	0
T223	0	19827	0	0
T224	0	7543	0	0
T225	0	14037	0	0
T226	0	13064	0	0
T227	0	12032	0	0
T228	0	7855	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	2806	0	0
T2	130466	196	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T225	0	224	0	0
T228	0	242	0	0
T229	0	508	0	0
T230	0	450	0	0
T231	0	304	0	0
T232	0	266	0	0
T233	0	205	0	0
T234	0	138	0	0
T235	0	35	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	3044	0	0
T2	130466	138	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T225	0	293	0	0
T228	0	315	0	0
T229	0	488	0	0
T230	0	521	0	0
T231	0	381	0	0
T232	0	342	0	0
T233	0	292	0	0
T234	0	140	0	0
T235	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	2701	0	0
T2	130466	130	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T5	671	0	0	0
T8	0	8	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T91	0	1	0	0
T92	0	6	0	0
T98	0	7	0	0
T225	0	209	0	0
T228	0	260	0	0
T229	0	385	0	0
T236	0	3	0	0
T237	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	3185	0	0
T2	130466	214	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T225	0	292	0	0
T228	0	321	0	0
T229	0	507	0	0
T230	0	464	0	0
T231	0	412	0	0
T232	0	397	0	0
T233	0	196	0	0
T234	0	170	0	0
T235	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	6083	0	0
T2	130466	460	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T51	0	37	0	0
T98	0	92	0	0
T198	0	93	0	0
T225	0	426	0	0
T228	0	301	0	0
T229	0	652	0	0
T230	0	889	0	0
T238	0	9	0	0
T239	0	19	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	3042	0	0
T2	130466	141	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T225	0	232	0	0
T228	0	253	0	0
T229	0	408	0	0
T230	0	388	0	0
T231	0	383	0	0
T232	0	326	0	0
T233	0	210	0	0
T234	0	121	0	0
T235	0	16	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10749503	3370	0	0
T2	130466	156	0	0
T3	2872	0	0	0
T4	135352	0	0	0
T5	671	0	0	0
T9	1810	0	0	0
T10	2839	0	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T225	0	278	0	0
T228	0	268	0	0
T229	0	457	0	0
T230	0	487	0	0
T231	0	451	0	0
T232	0	390	0	0
T233	0	224	0	0
T234	0	134	0	0
T235	0	9	0	0