Group : tb.dut.u_edn_cov_if::edn_cfg_cg
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Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 100.00 1 100 1 64 64




Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 21 0 21 100.00


Variables for Group Instance edn_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 0 2 100.00 100 1 1 0
cp_num_endpoints 7 0 7 100.00 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 0 21 100.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
boot_req_mode 157 1 T19 1 T31 1 T43 1
auto_req_mode 119 1 T15 1 T16 1 T17 1
sw_mode 2168 1 T2 1 T53 1 T30 1



Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 303 1 T2 1 T19 1 T31 1
single 97 1 T17 1 T224 1 T35 1



Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1149 1 T19 1 T31 1 T53 1
auto[2] 161 1 T43 1 T93 1 T298 1
auto[3] 121 1 T68 1 T299 1 T300 1
auto[4] 71 1 T301 1 T302 1 T303 1
auto[5] 75 1 T29 66 T304 1 T305 1
auto[6] 68 1 T75 1 T38 1 T35 1
auto[7] 799 1 T2 1 T30 1 T63 7



Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 0 21 100.00


Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpointscp_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] boot_req_mode 95 1 T19 1 T31 1 T61 1
auto[1] auto_req_mode 77 1 T15 1 T16 1 T57 1
auto[1] sw_mode 977 1 T53 1 T44 10 T62 1
auto[2] boot_req_mode 3 1 T43 1 T306 1 T307 1
auto[2] auto_req_mode 4 1 T93 1 T308 1 T309 1
auto[2] sw_mode 154 1 T298 1 T310 9 T311 1
auto[3] boot_req_mode 7 1 T300 1 T312 1 T313 1
auto[3] auto_req_mode 2 1 T299 1 T314 1 - -
auto[3] sw_mode 112 1 T68 1 T315 1 T316 1
auto[4] boot_req_mode 2 1 T301 1 T302 1 - -
auto[4] auto_req_mode 5 1 T303 1 T317 1 T318 1
auto[4] sw_mode 64 1 T319 1 T226 59 T320 1
auto[5] boot_req_mode 2 1 T321 1 T322 1 - -
auto[5] auto_req_mode 3 1 T304 1 T323 1 T324 1
auto[5] sw_mode 70 1 T29 66 T305 1 T325 1
auto[6] boot_req_mode 8 1 T326 1 T327 1 T328 1
auto[6] auto_req_mode 3 1 T38 1 T35 1 T329 1
auto[6] sw_mode 57 1 T75 1 T278 1 T330 1
auto[7] boot_req_mode 40 1 T37 1 T34 1 T80 1
auto[7] auto_req_mode 25 1 T17 1 T10 1 T331 1
auto[7] sw_mode 734 1 T2 1 T30 1 T63 7

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