Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

309345

1

T1

35

T2

20

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	208767	1			T1	35		T2	327		T3	61
values[0x0]	124842	1			T1	24		T2	8		T3	9
values[0x1]	139016	1			T1	15		T2	11		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	110069	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

362556

1

T1

47

T2

119

T3

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1240	1			T2	2		T5	6		T63	2
valid_sources[0x01]	1604	1			T2	6		T5	3		T6	1
valid_sources[0x02]	2082	1			T5	4		T63	2		T67	2
valid_sources[0x03]	1830	1			T2	3		T3	1		T5	8
valid_sources[0x04]	1787	1			T5	3		T61	1		T63	2
valid_sources[0x05]	2664	1			T2	1		T5	3		T20	4
valid_sources[0x06]	2138	1			T2	1		T3	1		T5	6
valid_sources[0x07]	1934	1			T2	7		T5	5		T31	1
valid_sources[0x08]	1737	1			T2	1		T5	2		T8	1
valid_sources[0x09]	2326	1			T2	2		T3	1		T5	8
valid_sources[0x0a]	2010	1			T2	3		T5	1		T31	2
valid_sources[0x0b]	1489	1			T2	2		T5	1		T6	2
valid_sources[0x0c]	1570	1			T5	4		T6	1		T63	4
valid_sources[0x0d]	1642	1			T2	1		T5	3		T63	4
valid_sources[0x0e]	2173	1			T2	1		T5	3		T53	1
valid_sources[0x0f]	1659	1			T2	1		T5	5		T33	2
valid_sources[0x10]	2432	1			T2	1		T5	4		T63	1
valid_sources[0x11]	1297	1			T2	2		T5	3		T8	1
valid_sources[0x12]	1648	1			T2	2		T5	5		T63	1
valid_sources[0x13]	2377	1			T1	8		T6	1		T53	2
valid_sources[0x14]	1535	1			T2	1		T4	3		T5	6
valid_sources[0x15]	1568	1			T2	5		T5	3		T8	2
valid_sources[0x16]	1919	1			T5	3		T31	1		T61	1
valid_sources[0x17]	1977	1			T2	3		T5	3		T6	1
valid_sources[0x18]	1324	1			T5	3		T31	1		T61	1
valid_sources[0x19]	2987	1			T1	24		T2	2		T5	2
valid_sources[0x1a]	1486	1			T2	3		T63	3		T45	1
valid_sources[0x1b]	1428	1			T4	2		T5	4		T31	1
valid_sources[0x1c]	1843	1			T2	4		T5	5		T8	3
valid_sources[0x1d]	1623	1			T5	4		T19	2		T61	1
valid_sources[0x1e]	2326	1			T5	3		T31	1		T63	1
valid_sources[0x1f]	1872	1			T2	1		T5	2		T63	5
valid_sources[0x20]	1529	1			T2	1		T5	2		T8	1
valid_sources[0x21]	1379	1			T2	3		T5	2		T6	2
valid_sources[0x22]	1572	1			T2	1		T5	3		T8	1
valid_sources[0x23]	1676	1			T1	3		T2	2		T5	4
valid_sources[0x24]	2242	1			T2	1		T5	2		T61	1
valid_sources[0x25]	1654	1			T5	3		T6	1		T61	1
valid_sources[0x26]	1603	1			T2	1		T5	2		T31	2
valid_sources[0x27]	2086	1			T2	1		T5	2		T6	1
valid_sources[0x28]	1530	1			T6	1		T61	1		T63	3
valid_sources[0x29]	2115	1			T2	3		T5	3		T53	1
valid_sources[0x2a]	2127	1			T5	3		T6	1		T31	1
valid_sources[0x2b]	1830	1			T2	1		T5	4		T8	2
valid_sources[0x2c]	1652	1			T2	2		T4	1		T5	3
valid_sources[0x2d]	1371	1			T2	1		T4	1		T5	5
valid_sources[0x2e]	1672	1			T2	4		T61	1		T102	1
valid_sources[0x2f]	1929	1			T2	1		T5	3		T8	1
valid_sources[0x30]	1448	1			T2	1		T5	8		T45	1
valid_sources[0x31]	2635	1			T2	1		T5	1		T6	1
valid_sources[0x32]	1927	1			T2	1		T5	5		T33	2
valid_sources[0x33]	1711	1			T2	2		T5	5		T31	1
valid_sources[0x34]	1383	1			T5	4		T31	1		T61	1
valid_sources[0x35]	1885	1			T5	4		T63	1		T45	3
valid_sources[0x36]	1599	1			T4	1		T5	4		T67	1
valid_sources[0x37]	1822	1			T31	4		T63	1		T39	1
valid_sources[0x38]	1494	1			T2	3		T4	2		T5	4
valid_sources[0x39]	1821	1			T3	3		T5	6		T61	1
valid_sources[0x3a]	1336	1			T5	8		T53	1		T63	1
valid_sources[0x3b]	1706	1			T1	3		T5	5		T31	1
valid_sources[0x3c]	1884	1			T3	1		T5	3		T31	3
valid_sources[0x3d]	1825	1			T2	3		T5	4		T63	2
valid_sources[0x3e]	1542	1			T2	1		T3	11		T5	2
valid_sources[0x3f]	1367	1			T61	1		T63	1		T67	1
valid_sources[0x40]	1837	1			T2	1		T4	1		T5	1
valid_sources[0x41]	2256	1			T5	3		T8	1		T53	1
valid_sources[0x42]	1677	1			T5	3		T31	1		T67	1
valid_sources[0x43]	2025	1			T2	6		T5	4		T20	1
valid_sources[0x44]	1523	1			T2	1		T5	3		T63	3
valid_sources[0x45]	2033	1			T5	2		T63	1		T67	1
valid_sources[0x46]	1608	1			T2	1		T3	1		T5	2
valid_sources[0x47]	2135	1			T5	4		T63	2		T45	2
valid_sources[0x48]	2218	1			T2	2		T5	4		T43	16
valid_sources[0x49]	1702	1			T4	2		T5	3		T63	5
valid_sources[0x4a]	1348	1			T2	1		T4	1		T5	5
valid_sources[0x4b]	1881	1			T2	3		T5	4		T7	20
valid_sources[0x4c]	1914	1			T2	1		T5	5		T63	2
valid_sources[0x4d]	2142	1			T2	4		T3	1		T4	1
valid_sources[0x4e]	1272	1			T2	3		T4	1		T5	3
valid_sources[0x4f]	1677	1			T3	3		T5	4		T6	1
valid_sources[0x50]	1802	1			T3	3		T5	8		T6	1
valid_sources[0x51]	1751	1			T2	1		T5	5		T20	5
valid_sources[0x52]	2083	1			T2	4		T3	2		T5	2
valid_sources[0x53]	1936	1			T5	2		T8	1		T31	1
valid_sources[0x54]	1750	1			T2	1		T5	6		T61	4
valid_sources[0x55]	1974	1			T2	3		T5	2		T6	1
valid_sources[0x56]	1504	1			T5	1		T6	1		T63	2
valid_sources[0x57]	1729	1			T5	4		T31	1		T63	1
valid_sources[0x58]	2002	1			T1	23		T2	1		T5	5
valid_sources[0x59]	1886	1			T2	2		T5	7		T63	1
valid_sources[0x5a]	1715	1			T5	5		T7	1		T63	1
valid_sources[0x5b]	1670	1			T5	2		T8	5		T6	1
valid_sources[0x5c]	1708	1			T2	2		T5	5		T6	1
valid_sources[0x5d]	2273	1			T5	4		T63	3		T39	2
valid_sources[0x5e]	1558	1			T5	3		T6	1		T53	2
valid_sources[0x5f]	1461	1			T2	1		T4	1		T5	2
valid_sources[0x60]	1383	1			T2	1		T5	4		T53	1
valid_sources[0x61]	1592	1			T2	1		T3	1		T4	1
valid_sources[0x62]	1911	1			T2	1		T4	1		T61	1
valid_sources[0x63]	1791	1			T2	1		T5	4		T6	1
valid_sources[0x64]	1973	1			T2	2		T3	1		T5	6
valid_sources[0x65]	1613	1			T2	1		T5	7		T45	1
valid_sources[0x66]	1687	1			T2	2		T5	2		T45	1
valid_sources[0x67]	1366	1			T4	2		T5	5		T31	1
valid_sources[0x68]	1583	1			T2	1		T5	7		T45	2
valid_sources[0x69]	1356	1			T2	2		T5	4		T6	1
valid_sources[0x6a]	1630	1			T2	2		T5	5		T53	3
valid_sources[0x6b]	1662	1			T2	2		T5	8		T8	1
valid_sources[0x6c]	1323	1			T2	2		T5	3		T6	2
valid_sources[0x6d]	1644	1			T2	1		T5	4		T63	1
valid_sources[0x6e]	1568	1			T2	2		T5	1		T53	1
valid_sources[0x6f]	1875	1			T5	4		T8	2		T63	1
valid_sources[0x70]	1530	1			T2	2		T5	4		T31	1
valid_sources[0x71]	1267	1			T3	2		T5	3		T6	1
valid_sources[0x72]	2052	1			T63	1		T16	1		T74	1
valid_sources[0x73]	1889	1			T5	5		T8	7		T53	2
valid_sources[0x74]	1444	1			T2	1		T5	4		T53	1
valid_sources[0x75]	1500	1			T5	5		T66	1		T63	1
valid_sources[0x76]	1753	1			T1	1		T2	1		T5	4
valid_sources[0x77]	2455	1			T2	2		T3	5		T5	3
valid_sources[0x78]	1551	1			T2	3		T4	1		T5	2
valid_sources[0x79]	2434	1			T2	2		T3	2		T5	5
valid_sources[0x7a]	1972	1			T2	3		T3	3		T5	4
valid_sources[0x7b]	1582	1			T2	1		T5	5		T6	1
valid_sources[0x7c]	1943	1			T4	3		T5	3		T31	1
valid_sources[0x7d]	2517	1			T2	1		T3	1		T5	4
valid_sources[0x7e]	1567	1			T2	2		T5	8		T8	1
valid_sources[0x7f]	1260	1			T2	3		T5	7		T39	1
valid_sources[0x80]	1918	1			T2	4		T5	5		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

84207

1

T1

8

T2

6

T3

3

values[0x0]

all_enables

biggest_size

113889

1

T1

17

T2

7

T3

5

values[0x1]

all_enables

biggest_size

111249

1

T1

10

T2

7

T4

24