Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1820	1			T2	3		T31	1		T43	2
non_zero_bins[1]	1263	1			T31	1		T30	1		T44	3
zero	6299	1			T1	3		T2	1		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	306	1			T2	1		T43	1		T44	4
uni	2306	1			T2	1		T31	3		T43	2
gen	3101	1			T1	2		T2	1		T3	1
res	642	1			T44	1		T45	1		T15	2
ins	3027	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6088

1

T2

1

T3

2

T19

3

mubi_true

3294

1

T1

3

T2

3

T20

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

36

1

T39

1

T73

1

T95

1

pass

9346

1

T1

3

T2

4

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	73	1			T44	1		T233	1		T27	3
upd	non_zero_bins[0]	pass	mubi_true	78	1			T2	1		T44	3		T61	1
upd	non_zero_bins[1]	pass	mubi_false	51	1			T27	4		T94	1		T240	1
upd	non_zero_bins[1]	pass	mubi_true	56	1			T21	1		T37	1		T27	1
upd	zero	pass	mubi_false	20	1			T91	1		T98	1		T274	1
upd	zero	pass	mubi_true	28	1			T43	1		T27	2		T41	1
uni	zero	pass	mubi_false	1778	1			T2	1		T31	2		T43	2
uni	zero	pass	mubi_true	528	1			T31	1		T44	3		T63	4
gen	non_zero_bins[0]	pass	mubi_false	340	1			T43	1		T44	2		T61	1
gen	non_zero_bins[0]	pass	mubi_true	321	1			T2	1		T44	2		T63	1
gen	non_zero_bins[1]	pass	mubi_false	277	1			T31	1		T45	1		T17	3
gen	non_zero_bins[1]	pass	mubi_true	226	1			T30	1		T44	2		T16	3
gen	zero	fail	mubi_false	31	1			T39	1		T73	1		T95	1
gen	zero	pass	mubi_false	1250	1			T3	1		T19	1		T8	1
gen	zero	pass	mubi_true	656	1			T1	2		T20	2		T8	2
res	non_zero_bins[0]	pass	mubi_false	160	1			T44	1		T27	1		T29	2
res	non_zero_bins[0]	pass	mubi_true	142	1			T17	2		T27	1		T68	1
res	non_zero_bins[1]	pass	mubi_false	103	1			T45	1		T57	3		T27	2
res	non_zero_bins[1]	pass	mubi_true	104	1			T15	2		T16	2		T38	2
res	zero	fail	mubi_false	5	1			T148	1		T149	1		T150	1
res	zero	pass	mubi_false	65	1			T74	1		T27	2		T29	3
res	zero	pass	mubi_true	63	1			T27	1		T29	2		T79	6
ins	non_zero_bins[0]	pass	mubi_false	357	1			T43	1		T30	1		T44	3
ins	non_zero_bins[0]	pass	mubi_true	349	1			T2	1		T31	1		T44	2
ins	non_zero_bins[1]	pass	mubi_false	218	1			T63	2		T27	8		T28	1
ins	non_zero_bins[1]	pass	mubi_true	228	1			T44	1		T45	1		T17	1
ins	zero	pass	mubi_false	1360	1			T3	1		T19	2		T8	1
ins	zero	pass	mubi_true	515	1			T1	1		T20	1		T8	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded