Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T20,T66
1	1	Covered	T1,T19,T20

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T4,T8,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T20,T8
1	0	Covered	T4,T5,T6

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T20,T8
1	Covered	T4,T5,T6

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T20,T8
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T6

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T8,T6,T7
AutoCaptGenCnt	143	Covered	T8,T9,T6
AutoCaptReseedCnt	141	Covered	T8,T6,T15
AutoDispatch	125	Covered	T8,T9,T6
AutoFirstAckWait	119	Covered	T8,T9,T6
AutoLoadIns	69	Covered	T4,T8,T9
AutoSendGenCmd	150	Covered	T8,T6,T7
AutoSendReseedCmd	162	Covered	T15,T16,T17
BootDone	98	Covered	T19,T9,T31
BootGenAckWait	90	Covered	T19,T9,T31
BootInsAckWait	80	Covered	T1,T19,T20
BootLoadGen	85	Covered	T19,T9,T31
BootLoadIns	65	Covered	T1,T19,T20
BootLoadUni	102	Covered	T9,T31,T43
BootPulse	94	Covered	T19,T9,T31
BootUniAckWait	107	Covered	T9,T31,T43
Error	188	Covered	T4,T5,T6
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T20,T8
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T8,T6,T15
AutoAckWait->Error	188	Covered	T7,T47,T109
AutoAckWait->Idle	211	Covered	T57,T96,T79
AutoAckWait->RejectCsrngEntropy	188	Covered	T39,T95,T74
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T8,T6,T7
AutoCaptGenCnt->Error	188	Covered	T48,T110,T111
AutoCaptGenCnt->Idle	211	Covered	T112,T113,T114
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T9,T70,T115
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T15,T16,T17
AutoCaptReseedCnt->Error	188	Covered	T6,T18,T116
AutoCaptReseedCnt->Idle	211	Covered	T117,T118,T119
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T8,T120,T121
AutoDispatch->AutoCaptGenCnt	143	Covered	T8,T9,T6
AutoDispatch->AutoCaptReseedCnt	141	Covered	T8,T6,T15
AutoDispatch->Error	188	Covered	T122,T123,T124
AutoDispatch->Idle	138	Covered	T15,T16,T17
AutoDispatch->RejectCsrngEntropy	188	Covered	T125,T126,T127
AutoFirstAckWait->AutoDispatch	125	Covered	T8,T9,T6
AutoFirstAckWait->Error	188	Not Covered
AutoFirstAckWait->Idle	211	Covered	T128,T129,T130
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T99,T76,T100
AutoLoadIns->AutoFirstAckWait	119	Covered	T8,T9,T6
AutoLoadIns->Error	188	Covered	T4,T67,T131
AutoLoadIns->Idle	211	Covered	T4,T8,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T132,T133,T134
AutoSendGenCmd->AutoAckWait	156	Covered	T8,T6,T7
AutoSendGenCmd->Error	188	Covered	T135,T136,T137
AutoSendGenCmd->Idle	211	Covered	T138,T139,T140
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T78,T72,T141
AutoSendReseedCmd->AutoAckWait	168	Covered	T15,T16,T17
AutoSendReseedCmd->Error	188	Covered	T142,T143,T144
AutoSendReseedCmd->Idle	211	Covered	T145,T146,T147
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T148,T149,T150
BootDone->BootLoadUni	102	Covered	T9,T31,T43
BootDone->Error	188	Covered	T66,T52,T151
BootDone->Idle	211	Covered	T152,T153,T154
BootDone->RejectCsrngEntropy	188	Covered	T71,T155,T156
BootGenAckWait->BootPulse	94	Covered	T19,T9,T31
BootGenAckWait->Error	188	Not Covered
BootGenAckWait->Idle	211	Covered	T157,T158,T159
BootGenAckWait->RejectCsrngEntropy	188	Covered	T73,T77,T97
BootInsAckWait->BootLoadGen	85	Covered	T19,T9,T31
BootInsAckWait->Error	188	Covered	T160,T159,T161
BootInsAckWait->Idle	211	Covered	T66,T160,T162
BootInsAckWait->RejectCsrngEntropy	188	Covered	T1,T20,T163
BootLoadGen->BootGenAckWait	90	Covered	T19,T9,T31
BootLoadGen->Error	188	Covered	T162
BootLoadGen->Idle	211	Covered	T19,T32,T164
BootLoadGen->RejectCsrngEntropy	188	Covered	T165,T166,T167
BootLoadIns->BootInsAckWait	80	Covered	T1,T19,T20
BootLoadIns->Error	188	Covered	T168,T169,T170
BootLoadIns->Idle	211	Covered	T171
BootLoadIns->RejectCsrngEntropy	188	Covered	T102,T172,T173
BootLoadUni->BootUniAckWait	107	Covered	T9,T31,T43
BootLoadUni->Error	188	Covered	T174,T175,T176
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T177,T178,T179
BootPulse->BootDone	98	Covered	T19,T9,T31
BootPulse->Error	188	Covered	T180
BootPulse->Idle	211	Covered	T181,T182,T183
BootPulse->RejectCsrngEntropy	188	Covered	T40,T184,T185
BootUniAckWait->Error	188	Covered	T186,T187
BootUniAckWait->Idle	112	Covered	T9,T31,T43
BootUniAckWait->RejectCsrngEntropy	188	Covered	T36,T92,T188
Idle->AutoLoadIns	69	Covered	T4,T8,T9
Idle->BootLoadIns	65	Covered	T1,T19,T20
Idle->Error	188	Covered	T5,T13,T14
Idle->RejectCsrngEntropy	188	Covered	T1,T8,T9
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T49,T189,T190
RejectCsrngEntropy->Idle	211	Covered	T1,T20,T8
SWPortMode->Error	188	Covered	T5,T13,T191
SWPortMode->Idle	211	Covered	T1,T3,T5
SWPortMode->RejectCsrngEntropy	188	Covered	T20,T39,T73

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T20
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T20
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T20
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T20
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T9,T31
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T19,T9,T31
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T19,T9,T31
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T9,T31
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T9,T31,T43
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T19,T9,T66
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T31,T43
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T31,T43,T61
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T9,T31,T43
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T6
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T6
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T6
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T6,T39
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T6,T7
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T15,T16,T17
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T6,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T9,T6
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T6
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T6,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T7,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T6,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T16,T17
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T15,T16,T17
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T8
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T46,T13

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T6
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T20,T8
0	-	-	1	Covered	T1,T3,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	11097801	149465	0	0
FpvSecCmErrorStEscalate_A	11097801	150761	0	0
u_state_regs_A	11057491	10857432	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	149465	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	324	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	716	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1049	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1100	0	0
T67	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	150761	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	325	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	717	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1050	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1101	0	0
T67	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11057491	10857432	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1152	976	0	0
T4	1988	1870	0	0
T5	42906	21480	0	0
T6	602	459	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0