Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T20
DataWait	75	Covered	T2,T3,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T182,T183
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T20
DataWait->AckPls	80	Covered	T2,T3,T20
DataWait->Disabled	107	Covered	T19,T32,T28
DataWait->Error	99	Covered	T47,T48,T49
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T67,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T20
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T20
Idle	-	1	0	-	Covered	T2,T3,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T20
DataWait	-	-	-	0	Covered	T2,T20,T8
AckPls	-	-	-	-	Covered	T2,T3,T20
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T7,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	77684607	1061805	0	0
FpvSecCmErrorStEscalate_A	77684607	1070877	0	0
u_state_regs_A	77644297	76243884	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77684607	1061805	0	0
T4	15302	7637	0	0
T5	300342	98805	0	0
T6	5719	2254	0	0
T7	0	2218	0	0
T8	21595	0	0	0
T9	10108	0	0	0
T13	0	150878	0	0
T18	0	4962	0	0
T19	7511	0	0	0
T20	16765	0	0	0
T31	16807	0	0	0
T43	11396	0	0	0
T46	0	7693	0	0
T47	0	1204	0	0
T53	6545	0	0	0
T66	0	7650	0	0
T67	0	2470	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77684607	1070877	0	0
T4	15302	7644	0	0
T5	300342	100625	0	0
T6	5719	2261	0	0
T7	0	2225	0	0
T8	21595	0	0	0
T9	10108	0	0	0
T13	0	152698	0	0
T18	0	4969	0	0
T19	7511	0	0	0
T20	16765	0	0	0
T31	16807	0	0	0
T43	11396	0	0	0
T46	0	7700	0	0
T47	0	1211	0	0
T53	6545	0	0	0
T66	0	7657	0	0
T67	0	2477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77644297	76243884	0	0
T1	20223	19852	0	0
T2	12684	12005	0	0
T3	8148	6916	0	0
T4	15104	14278	0	0
T5	300342	150360	0	0
T6	5504	4503	0	0
T8	21595	21245	0	0
T9	10108	9632	0	0
T19	7511	7126	0	0
T20	16765	16261	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T6
DataWait	75	Covered	T2,T3,T6
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T6
DataWait->AckPls	80	Covered	T2,T3,T6
DataWait->Disabled	107	Covered	T28,T29,T194
DataWait->Error	99	Covered	T47,T48,T49
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T13,T168
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T6
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T6
Idle	-	1	0	-	Covered	T2,T3,T6
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T6
DataWait	-	-	-	0	Covered	T2,T6,T31
AckPls	-	-	-	-	Covered	T2,T3,T6
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T7,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11097801	150015	0	0
FpvSecCmErrorStEscalate_A	11097801	151311	0	0
u_state_regs_A	11057491	10857432	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	150015	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	274	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	666	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1099	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1050	0	0
T67	0	310	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	151311	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	275	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	667	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1100	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1051	0	0
T67	0	311	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11057491	10857432	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1152	976	0	0
T4	1988	1870	0	0
T5	42906	21480	0	0
T6	602	459	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T8,T30
DataWait	75	Covered	T2,T8,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T8,T30
DataWait->AckPls	80	Covered	T2,T8,T30
DataWait->Disabled	107	Covered	T32,T195,T196
DataWait->Error	99	Covered	T52,T131,T174
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T67,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T8,T30
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T8,T30
Idle	-	1	0	-	Covered	T2,T8,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T8,T30
DataWait	-	-	-	0	Covered	T2,T8,T30
AckPls	-	-	-	-	Covered	T2,T8,T30
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11097801	151965	0	0
FpvSecCmErrorStEscalate_A	11097801	153261	0	0
u_state_regs_A	11097801	10897742	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	151965	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	324	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	716	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1099	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1100	0	0
T67	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	153261	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	325	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	717	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1100	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1101	0	0
T67	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T8,T30
DataWait	75	Covered	T2,T8,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T8,T30
DataWait->AckPls	80	Covered	T2,T8,T30
DataWait->Disabled	107	Covered	T164
DataWait->Error	99	Covered	T111,T197,T176
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T67,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T8,T30
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T8,T30
Idle	-	1	0	-	Covered	T2,T8,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T8,T30
DataWait	-	-	-	0	Covered	T2,T30,T33
AckPls	-	-	-	-	Covered	T2,T8,T30
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11097801	151965	0	0
FpvSecCmErrorStEscalate_A	11097801	153261	0	0
u_state_regs_A	11097801	10897742	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	151965	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	324	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	716	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1099	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1100	0	0
T67	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	153261	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	325	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	717	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1100	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1101	0	0
T67	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T30,T39
DataWait	75	Covered	T2,T30,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T30,T39
DataWait->AckPls	80	Covered	T2,T30,T39
DataWait->Disabled	107	Covered	T198,T199
DataWait->Error	99	Covered	T7,T66,T200
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T67,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T30,T7
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T30,T39
Idle	-	1	0	-	Covered	T2,T30,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T30,T39
DataWait	-	-	-	0	Covered	T2,T30,T7
AckPls	-	-	-	-	Covered	T2,T30,T39
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11097801	151965	0	0
FpvSecCmErrorStEscalate_A	11097801	153261	0	0
u_state_regs_A	11097801	10897742	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	151965	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	324	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	716	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1099	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1100	0	0
T67	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	153261	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	325	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	717	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1100	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1101	0	0
T67	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T30,T40
DataWait	75	Covered	T2,T4,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T30,T40
DataWait->AckPls	80	Covered	T2,T30,T40
DataWait->Disabled	107	Covered	T201,T202
DataWait->Error	99	Covered	T4,T203,T204
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T67,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T4,T30
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T30,T40
Idle	-	1	0	-	Covered	T2,T4,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T30,T40
DataWait	-	-	-	0	Covered	T2,T4,T30
AckPls	-	-	-	-	Covered	T2,T30,T40
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11097801	151965	0	0
FpvSecCmErrorStEscalate_A	11097801	153261	0	0
u_state_regs_A	11097801	10897742	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	151965	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	324	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	716	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1099	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1100	0	0
T67	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	153261	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	325	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	717	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1100	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1101	0	0
T67	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T20,T30
DataWait	75	Covered	T2,T20,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T183
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T20,T30
DataWait->AckPls	80	Covered	T2,T20,T30
DataWait->Disabled	107	Covered	T158,T139
DataWait->Error	99	Covered	T205,T206,T207
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T67,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T20,T30
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T20,T30
Idle	-	1	0	-	Covered	T2,T20,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T20,T30
DataWait	-	-	-	0	Covered	T2,T20,T30
AckPls	-	-	-	-	Covered	T2,T20,T30
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11097801	151965	0	0
FpvSecCmErrorStEscalate_A	11097801	153261	0	0
u_state_regs_A	11097801	10897742	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	151965	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	324	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	716	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1099	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1100	0	0
T67	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	153261	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	325	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	717	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1100	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1101	0	0
T67	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T19
DataWait	75	Covered	T1,T2,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T182
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T19
DataWait->AckPls	80	Covered	T1,T2,T19
DataWait->Disabled	107	Covered	T19,T112,T138
DataWait->Error	99	Covered	T180,T208
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T13,T14
EndPointClear->Disabled	107	Covered	T171,T192,T193
EndPointClear->Error	99	Covered	T5,T67,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T19
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T19
Idle	-	1	0	-	Covered	T1,T2,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T19
DataWait	-	-	-	0	Covered	T1,T2,T19
AckPls	-	-	-	-	Covered	T1,T2,T19
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11097801	151965	0	0
FpvSecCmErrorStEscalate_A	11097801	153261	0	0
u_state_regs_A	11097801	10897742	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	151965	0	0
T4	2186	1091	0	0
T5	42906	14115	0	0
T6	817	322	0	0
T7	0	324	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21554	0	0
T18	0	716	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1099	0	0
T47	0	172	0	0
T53	935	0	0	0
T66	0	1100	0	0
T67	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	153261	0	0
T4	2186	1092	0	0
T5	42906	14375	0	0
T6	817	323	0	0
T7	0	325	0	0
T8	3085	0	0	0
T9	1444	0	0	0
T13	0	21814	0	0
T18	0	717	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T31	2401	0	0	0
T43	1628	0	0	0
T46	0	1100	0	0
T47	0	173	0	0
T53	935	0	0	0
T66	0	1101	0	0
T67	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0