Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T81,T82
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T6

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	21390820	535655	0	0
DepthKnown_A	22195602	21795484	0	0
RvalidKnown_A	22195602	21795484	0	0
WreadyKnown_A	22195602	21795484	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	21740224	637894	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21390820	535655	0	0
T1	5778	237	0	0
T2	3624	0	0	0
T3	648	0	0	0
T4	684	232	0	0
T5	1224	0	0	0
T6	354	91	0	0
T7	0	442	0	0
T8	6170	1294	0	0
T9	2888	292	0	0
T15	0	9583	0	0
T18	0	164	0	0
T19	2146	0	0	0
T20	4790	0	0	0
T39	0	407	0	0
T67	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22195602	21795484	0	0
T1	5778	5672	0	0
T2	3624	3430	0	0
T3	2332	1980	0	0
T4	4372	4136	0	0
T5	85812	42960	0	0
T6	1634	1348	0	0
T8	6170	6070	0	0
T9	2888	2752	0	0
T19	2146	2036	0	0
T20	4790	4646	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22195602	21795484	0	0
T1	5778	5672	0	0
T2	3624	3430	0	0
T3	2332	1980	0	0
T4	4372	4136	0	0
T5	85812	42960	0	0
T6	1634	1348	0	0
T8	6170	6070	0	0
T9	2888	2752	0	0
T19	2146	2036	0	0
T20	4790	4646	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22195602	21795484	0	0
T1	5778	5672	0	0
T2	3624	3430	0	0
T3	2332	1980	0	0
T4	4372	4136	0	0
T5	85812	42960	0	0
T6	1634	1348	0	0
T8	6170	6070	0	0
T9	2888	2752	0	0
T19	2146	2036	0	0
T20	4790	4646	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	21740224	637894	0	0
T1	5778	237	0	0
T2	3624	0	0	0
T3	2332	7	0	0
T4	4372	1592	0	0
T5	1224	0	0	0
T6	1634	755	0	0
T7	0	2016	0	0
T8	6170	1294	0	0
T9	2888	292	0	0
T15	0	4787	0	0
T19	2146	0	0	0
T20	4790	0	0	0
T39	0	407	0	0
T66	0	258	0	0
T67	0	582	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T47,T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T83
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T8,T6,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10695410	262607	0	0
DepthKnown_A	11097801	10897742	0	0
RvalidKnown_A	11097801	10897742	0	0
WreadyKnown_A	11097801	10897742	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	10870112	313121	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695410	262607	0	0
T1	2889	53	0	0
T2	1812	0	0	0
T3	324	0	0	0
T4	342	99	0	0
T5	612	0	0	0
T6	177	39	0	0
T7	0	229	0	0
T8	3085	594	0	0
T9	1444	147	0	0
T15	0	4787	0	0
T18	0	69	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T39	0	205	0	0
T67	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	10870112	313121	0	0
T1	2889	53	0	0
T2	1812	0	0	0
T3	1166	0	0	0
T4	2186	760	0	0
T5	612	0	0	0
T6	817	363	0	0
T7	0	944	0	0
T8	3085	594	0	0
T9	1444	147	0	0
T15	0	4787	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T39	0	205	0	0
T66	0	130	0	0
T67	0	273	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T81,T82,T84
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T85,T86,T87
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10695410	273048	0	0
DepthKnown_A	11097801	10897742	0	0
RvalidKnown_A	11097801	10897742	0	0
WreadyKnown_A	11097801	10897742	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	10870112	324773	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695410	273048	0	0
T1	2889	184	0	0
T2	1812	0	0	0
T3	324	0	0	0
T4	342	133	0	0
T5	612	0	0	0
T6	177	52	0	0
T7	0	213	0	0
T8	3085	700	0	0
T9	1444	145	0	0
T15	0	4796	0	0
T18	0	95	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T39	0	202	0	0
T67	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11097801	10897742	0	0
T1	2889	2836	0	0
T2	1812	1715	0	0
T3	1166	990	0	0
T4	2186	2068	0	0
T5	42906	21480	0	0
T6	817	674	0	0
T8	3085	3035	0	0
T9	1444	1376	0	0
T19	1073	1018	0	0
T20	2395	2323	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	10870112	324773	0	0
T1	2889	184	0	0
T2	1812	0	0	0
T3	1166	7	0	0
T4	2186	832	0	0
T5	612	0	0	0
T6	817	392	0	0
T7	0	1072	0	0
T8	3085	700	0	0
T9	1444	145	0	0
T19	1073	0	0	0
T20	2395	0	0	0
T39	0	202	0	0
T66	0	128	0	0
T67	0	309	0	0