Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.40			85.40

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_count_max_reqs_cntr	70.79			70.79
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr	100.00			100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr	100.00			100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr	100.00			100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.79			70.79

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.79			70.79

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
70.79	70.79

tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	202	143	70.79
Total Bits 0->1	101	73	72.28
Total Bits 1->0	101	70	69.31

Ports	8	7	87.50
Port Bits	202	143	70.79
Port Bits 0->1	101	73	72.28
Port Bits 1->0	101	70	69.31

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[0]	Yes	Yes	*T4,*T6,*T7	Yes	T4,T8,T9	INPUT
set_cnt_i[3:1]	No	No		Yes	T10,T11,T12	INPUT
set_cnt_i[31:4]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T8,T6,T7	Yes	T8,T6,T7	INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T4,T5,T8	Yes	T4,T5,T8	OUTPUT
cnt_after_commit_o[31:0]	Yes	Yes	T4,T5,T8	Yes	T4,T5,T8	OUTPUT
err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORE	TOGGLE
100.00	100.00

tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORE	TOGGLE
100.00	100.00

tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORE	TOGGLE
100.00	100.00

tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T5,T13,T14	Yes	T5,T13,T14	OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	202	143	70.79
Total Bits 0->1	101	73	72.28
Total Bits 1->0	101	70	69.31

Ports	8	7	87.50
Port Bits	202	143	70.79
Port Bits 0->1	101	73	72.28
Port Bits 1->0	101	70	69.31

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[0]	Yes	Yes	*T4,*T6,*T7	Yes	T4,T8,T9	INPUT
set_cnt_i[3:1]	No	No		Yes	T10,T11,T12	INPUT
set_cnt_i[31:4]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T8,T6,T7	Yes	T8,T6,T7	INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T4,T5,T8	Yes	T4,T5,T8	OUTPUT
cnt_after_commit_o[31:0]	Yes	Yes	T4,T5,T8	Yes	T4,T5,T8	OUTPUT
err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T7,T15,T16	Yes	T7,T15,T16	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T5,T7,T15	Yes	T5,T7,T15	INPUT
incr_en_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
err_o	Yes	Yes	T5,T13,T14	Yes	T5,T13,T14	OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	INPUT
incr_en_i	Yes	Yes	T6,T15,T18	Yes	T6,T15,T18	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
err_o	Yes	Yes	T5,T13,T14	Yes	T5,T13,T14	OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
err_o	Yes	Yes	T5,T13,T14	Yes	T5,T13,T14	OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	34	34	100.00
Total Bits 0->1	17	17	100.00
Total Bits 1->0	17	17	100.00

Ports	9	9	100.00
Port Bits	34	34	100.00
Port Bits 0->1	17	17	100.00
Port Bits 1->0	17	17	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T16,T17,T10	Yes	T16,T17,T10	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	INPUT
incr_en_i	Yes	Yes	T8,T6,T7	Yes	T8,T6,T7	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T5,T8,T6	Yes	T5,T8,T6	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T5,T8,T6	Yes	T5,T8,T6	OUTPUT
err_o	Yes	Yes	T5,T13,T14	Yes	T5,T13,T14	OUTPUT