Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145481	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

282345

1

T1

3

T2

3617

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	187251	1			T1	1		T2	1132		T3	24
values[0x0]	113974	1			T1	2		T2	1365		T3	25
values[0x1]	126601	1			T1	3		T2	1603		T3	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	98613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

329213

1

T1

3

T2

3829

T3

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1934	1			T2	16		T4	24		T28	1
valid_sources[0x01]	1532	1			T2	16		T4	2		T24	8
valid_sources[0x02]	1969	1			T2	19		T4	48		T20	2
valid_sources[0x03]	2051	1			T2	15		T4	28		T24	3
valid_sources[0x04]	1644	1			T2	20		T4	30		T20	1
valid_sources[0x05]	1406	1			T2	18		T4	40		T24	2
valid_sources[0x06]	1660	1			T2	13		T4	32		T20	2
valid_sources[0x07]	1590	1			T2	22		T4	28		T24	5
valid_sources[0x08]	1865	1			T2	17		T4	41		T20	1
valid_sources[0x09]	1902	1			T2	11		T4	34		T20	3
valid_sources[0x0a]	1301	1			T2	13		T4	24		T20	3
valid_sources[0x0b]	1330	1			T2	13		T4	30		T24	8
valid_sources[0x0c]	1393	1			T2	14		T4	22		T24	4
valid_sources[0x0d]	1672	1			T2	8		T4	54		T27	1
valid_sources[0x0e]	1852	1			T2	11		T4	36		T24	4
valid_sources[0x0f]	1697	1			T2	8		T4	21		T20	4
valid_sources[0x10]	1893	1			T2	16		T4	62		T20	1
valid_sources[0x11]	1459	1			T2	14		T4	33		T20	3
valid_sources[0x12]	1966	1			T2	17		T4	17		T24	9
valid_sources[0x13]	1542	1			T2	11		T4	38		T24	2
valid_sources[0x14]	1252	1			T2	12		T4	22		T24	5
valid_sources[0x15]	1546	1			T2	14		T3	1		T4	34
valid_sources[0x16]	1450	1			T2	10		T4	37		T23	1
valid_sources[0x17]	1626	1			T2	14		T4	43		T24	2
valid_sources[0x18]	1597	1			T2	16		T4	15		T24	2
valid_sources[0x19]	1610	1			T2	17		T4	31		T24	2
valid_sources[0x1a]	1357	1			T2	19		T4	27		T24	1
valid_sources[0x1b]	1390	1			T2	22		T4	7		T29	3
valid_sources[0x1c]	1710	1			T2	17		T4	32		T31	1
valid_sources[0x1d]	1386	1			T2	12		T4	33		T54	20
valid_sources[0x1e]	1606	1			T2	16		T4	21		T24	5
valid_sources[0x1f]	1606	1			T2	15		T4	26		T20	4
valid_sources[0x20]	1463	1			T2	22		T4	59		T20	4
valid_sources[0x21]	1522	1			T2	11		T4	29		T24	3
valid_sources[0x22]	2302	1			T2	12		T4	21		T24	2
valid_sources[0x23]	1415	1			T2	15		T4	6		T29	1
valid_sources[0x24]	1846	1			T2	18		T4	12		T28	3
valid_sources[0x25]	1475	1			T2	17		T4	26		T24	5
valid_sources[0x26]	1550	1			T2	17		T4	28		T20	2
valid_sources[0x27]	1638	1			T2	22		T3	4		T4	36
valid_sources[0x28]	1318	1			T2	20		T4	43		T20	2
valid_sources[0x29]	1378	1			T2	11		T4	11		T29	5
valid_sources[0x2a]	2025	1			T2	15		T4	36		T24	3
valid_sources[0x2b]	1211	1			T2	12		T4	56		T20	1
valid_sources[0x2c]	1478	1			T2	9		T4	17		T20	1
valid_sources[0x2d]	1497	1			T2	11		T4	30		T24	1
valid_sources[0x2e]	1334	1			T2	10		T4	9		T27	1
valid_sources[0x2f]	1424	1			T2	16		T4	30		T29	1
valid_sources[0x30]	1487	1			T2	13		T3	5		T4	22
valid_sources[0x31]	1756	1			T2	23		T4	52		T24	6
valid_sources[0x32]	1861	1			T2	12		T3	1		T4	37
valid_sources[0x33]	1460	1			T2	19		T4	30		T24	2
valid_sources[0x34]	1514	1			T2	12		T4	24		T20	2
valid_sources[0x35]	1298	1			T2	17		T4	29		T20	8
valid_sources[0x36]	1719	1			T2	16		T3	7		T4	48
valid_sources[0x37]	1556	1			T2	16		T4	28		T24	4
valid_sources[0x38]	1963	1			T2	20		T4	44		T24	5
valid_sources[0x39]	1729	1			T2	16		T4	23		T29	1
valid_sources[0x3a]	1578	1			T2	18		T4	22		T24	5
valid_sources[0x3b]	2355	1			T2	23		T4	21		T24	6
valid_sources[0x3c]	1805	1			T2	12		T4	42		T20	2
valid_sources[0x3d]	1364	1			T2	20		T4	20		T24	8
valid_sources[0x3e]	1512	1			T2	23		T4	23		T21	1
valid_sources[0x3f]	1430	1			T2	21		T3	1		T4	18
valid_sources[0x40]	1686	1			T2	13		T4	21		T24	3
valid_sources[0x41]	1422	1			T2	17		T4	30		T20	4
valid_sources[0x42]	2303	1			T2	12		T3	6		T4	32
valid_sources[0x43]	1406	1			T2	12		T4	43		T29	2
valid_sources[0x44]	1856	1			T2	13		T4	42		T28	2
valid_sources[0x45]	1640	1			T2	20		T3	2		T4	17
valid_sources[0x46]	1517	1			T2	19		T3	3		T4	36
valid_sources[0x47]	1686	1			T2	11		T4	34		T20	8
valid_sources[0x48]	2586	1			T2	23		T4	13		T5	1
valid_sources[0x49]	1412	1			T2	14		T4	31		T20	1
valid_sources[0x4a]	1445	1			T2	19		T4	30		T20	1
valid_sources[0x4b]	1988	1			T2	23		T4	25		T20	3
valid_sources[0x4c]	1565	1			T2	15		T4	19		T29	1
valid_sources[0x4d]	1526	1			T2	13		T4	57		T22	1
valid_sources[0x4e]	1569	1			T2	13		T4	27		T21	1
valid_sources[0x4f]	1409	1			T2	17		T4	32		T21	1
valid_sources[0x50]	1750	1			T2	11		T4	17		T24	10
valid_sources[0x51]	2022	1			T2	5		T4	63		T24	5
valid_sources[0x52]	1513	1			T2	13		T4	26		T24	12
valid_sources[0x53]	1345	1			T2	12		T3	2		T4	16
valid_sources[0x54]	1462	1			T2	13		T4	23		T29	1
valid_sources[0x55]	1442	1			T2	11		T4	60		T20	3
valid_sources[0x56]	2141	1			T2	18		T4	22		T24	9
valid_sources[0x57]	1527	1			T2	14		T3	3		T4	34
valid_sources[0x58]	1711	1			T2	20		T4	20		T20	5
valid_sources[0x59]	2450	1			T2	23		T4	15		T20	2
valid_sources[0x5a]	2672	1			T2	20		T4	33		T20	1
valid_sources[0x5b]	1584	1			T2	19		T4	21		T20	1
valid_sources[0x5c]	1414	1			T2	19		T4	64		T24	2
valid_sources[0x5d]	1439	1			T2	15		T4	29		T28	1
valid_sources[0x5e]	1469	1			T2	13		T4	17		T24	5
valid_sources[0x5f]	1544	1			T2	10		T4	39		T20	3
valid_sources[0x60]	2116	1			T2	17		T4	20		T23	1
valid_sources[0x61]	2089	1			T2	20		T4	18		T20	1
valid_sources[0x62]	1896	1			T1	5		T2	13		T4	54
valid_sources[0x63]	1664	1			T2	18		T4	22		T29	1
valid_sources[0x64]	1794	1			T2	12		T4	21		T31	1
valid_sources[0x65]	1872	1			T2	16		T4	32		T24	12
valid_sources[0x66]	1750	1			T2	7		T4	25		T20	3
valid_sources[0x67]	1495	1			T2	22		T4	40		T29	2
valid_sources[0x68]	1172	1			T2	11		T4	18		T24	2
valid_sources[0x69]	1276	1			T2	14		T4	33		T20	1
valid_sources[0x6a]	1619	1			T2	13		T4	24		T24	10
valid_sources[0x6b]	1716	1			T2	16		T3	1		T4	45
valid_sources[0x6c]	1312	1			T2	23		T4	19		T29	1
valid_sources[0x6d]	1536	1			T2	19		T4	38		T24	10
valid_sources[0x6e]	2237	1			T2	20		T4	32		T24	1
valid_sources[0x6f]	1462	1			T2	17		T4	29		T24	6
valid_sources[0x70]	1943	1			T2	10		T4	9		T20	3
valid_sources[0x71]	1781	1			T2	12		T4	33		T20	2
valid_sources[0x72]	1587	1			T2	15		T4	28		T20	2
valid_sources[0x73]	1543	1			T2	8		T4	39		T24	4
valid_sources[0x74]	1887	1			T2	15		T4	31		T20	1
valid_sources[0x75]	1587	1			T2	13		T4	46		T20	1
valid_sources[0x76]	1477	1			T2	10		T4	41		T23	33
valid_sources[0x77]	1866	1			T2	10		T3	3		T4	17
valid_sources[0x78]	1800	1			T2	18		T4	36		T29	1
valid_sources[0x79]	1528	1			T2	21		T3	2		T4	13
valid_sources[0x7a]	1481	1			T2	14		T4	29		T24	1
valid_sources[0x7b]	2188	1			T2	20		T4	27		T20	2
valid_sources[0x7c]	1567	1			T2	14		T4	29		T20	1
valid_sources[0x7d]	2008	1			T2	20		T4	16		T24	11
valid_sources[0x7e]	2026	1			T2	15		T3	3		T4	48
valid_sources[0x7f]	2956	1			T2	13		T4	45		T23	14
valid_sources[0x80]	1299	1			T2	15		T4	29		T29	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76888

1

T2

946

T3

5

T4

1835

values[0x0]

all_enables

biggest_size

103666

1

T1

1

T2

1324

T3

23

values[0x1]

all_enables

biggest_size

101791

1

T1

2

T2

1347

T3

28