Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1687	1			T2	2		T3	5		T4	12
non_zero_bins[1]	1216	1			T3	2		T4	6		T8	3
zero	5845	1			T1	3		T2	6		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	289	1			T2	1		T4	3		T39	1
uni	2027	1			T2	2		T3	1		T4	23
gen	2994	1			T1	1		T2	2		T3	4
res	641	1			T3	2		T4	4		T20	1
ins	2797	1			T1	2		T2	3		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5533

1

T1

2

T2

6

T3

8

mubi_true

3215

1

T1

1

T2

2

T4

20

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

43

1

T100

1

T102

1

T73

1

pass

8705

1

T1

3

T2

8

T3

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	60	1			T2	1		T24	2		T44	1
upd	non_zero_bins[0]	pass	mubi_true	86	1			T4	2		T24	2		T43	1
upd	non_zero_bins[1]	pass	mubi_false	46	1			T229	1		T65	1		T90	1
upd	non_zero_bins[1]	pass	mubi_true	43	1			T38	1		T90	1		T91	2
upd	zero	pass	mubi_false	26	1			T4	1		T24	1		T68	1
upd	zero	pass	mubi_true	28	1			T39	1		T38	2		T89	1
uni	zero	pass	mubi_false	1537	1			T2	1		T3	1		T4	12
uni	zero	pass	mubi_true	490	1			T2	1		T4	11		T23	1
gen	non_zero_bins[0]	pass	mubi_false	311	1			T3	4		T4	4		T54	1
gen	non_zero_bins[0]	pass	mubi_true	319	1			T4	1		T20	1		T8	3
gen	non_zero_bins[1]	pass	mubi_false	259	1			T4	1		T8	1		T24	1
gen	non_zero_bins[1]	pass	mubi_true	261	1			T4	1		T18	3		T105	1
gen	zero	fail	mubi_false	37	1			T100	1		T102	1		T73	1
gen	zero	pass	mubi_false	1143	1			T2	1		T4	14		T22	1
gen	zero	pass	mubi_true	664	1			T1	1		T2	1		T4	1
res	non_zero_bins[0]	pass	mubi_false	160	1			T4	1		T20	1		T24	1
res	non_zero_bins[0]	pass	mubi_true	142	1			T4	1		T56	1		T98	1
res	non_zero_bins[1]	pass	mubi_false	103	1			T3	2		T4	1		T8	2
res	non_zero_bins[1]	pass	mubi_true	91	1			T12	3		T60	2		T271	2
res	zero	fail	mubi_false	6	1			T148	1		T149	1		T279	1
res	zero	pass	mubi_false	88	1			T4	1		T88	1		T280	2
res	zero	pass	mubi_true	51	1			T60	1		T88	1		T90	2
ins	non_zero_bins[0]	pass	mubi_false	306	1			T2	1		T3	1		T4	3
ins	non_zero_bins[0]	pass	mubi_true	303	1			T20	1		T8	1		T39	1
ins	non_zero_bins[1]	pass	mubi_false	213	1			T4	2		T54	1		T24	1
ins	non_zero_bins[1]	pass	mubi_true	200	1			T4	1		T23	1		T24	3
ins	zero	pass	mubi_false	1238	1			T1	2		T2	2		T4	15
ins	zero	pass	mubi_true	537	1			T4	2		T22	2		T23	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded