Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T25,T33,T34
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T36,T37
1	0	1	Covered	T3,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T8

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	19376714	1076255	0	0
DepthKnown_A	20168010	19814418	0	0
RvalidKnown_A	20168010	19814418	0	0
WreadyKnown_A	20168010	19814418	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	19746774	1168196	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19376714	1076255	0	0
T3	4800	1870	0	0
T4	480796	0	0	0
T5	766	415	0	0
T6	0	103	0	0
T8	13370	11237	0	0
T12	0	2698	0	0
T18	0	3596	0	0
T20	3868	0	0	0
T21	2462	0	0	0
T22	1836	0	0	0
T23	7378	0	0	0
T28	0	548	0	0
T29	5018	521	0	0
T31	832	0	0	0
T56	0	1914	0	0
T83	0	623	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20168010	19814418	0	0
T1	2086	1928	0	0
T2	207410	207216	0	0
T3	4800	4700	0	0
T4	480796	480574	0	0
T5	5050	4840	0	0
T8	13370	13200	0	0
T20	3868	3762	0	0
T21	2462	2316	0	0
T22	1836	1638	0	0
T23	7378	7240	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20168010	19814418	0	0
T1	2086	1928	0	0
T2	207410	207216	0	0
T3	4800	4700	0	0
T4	480796	480574	0	0
T5	5050	4840	0	0
T8	13370	13200	0	0
T20	3868	3762	0	0
T21	2462	2316	0	0
T22	1836	1638	0	0
T23	7378	7240	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20168010	19814418	0	0
T1	2086	1928	0	0
T2	207410	207216	0	0
T3	4800	4700	0	0
T4	480796	480574	0	0
T5	5050	4840	0	0
T8	13370	13200	0	0
T20	3868	3762	0	0
T21	2462	2316	0	0
T22	1836	1638	0	0
T23	7378	7240	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	19746774	1168196	0	0
T3	4800	1870	0	0
T4	480796	0	0	0
T5	5050	2274	0	0
T6	0	1600	0	0
T8	13370	11237	0	0
T12	0	2698	0	0
T14	0	224	0	0
T18	0	3596	0	0
T20	3868	0	0	0
T21	2462	0	0	0
T22	1836	0	0	0
T23	7378	0	0	0
T28	0	548	0	0
T29	5018	521	0	0
T31	3960	0	0	0
T56	0	1914	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T84
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T25,T33,T85
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T36
1	0	1	Covered	T3,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9688357	532479	0	0
DepthKnown_A	10084005	9907209	0	0
RvalidKnown_A	10084005	9907209	0	0
WreadyKnown_A	10084005	9907209	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	9873387	578547	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688357	532479	0	0
T3	2400	935	0	0
T4	240398	0	0	0
T5	383	146	0	0
T6	0	49	0	0
T8	6685	5614	0	0
T12	0	1296	0	0
T18	0	1801	0	0
T20	1934	0	0	0
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	0	0	0
T28	0	274	0	0
T29	2509	254	0	0
T31	416	0	0	0
T56	0	942	0	0
T83	0	307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	9873387	578547	0	0
T3	2400	935	0	0
T4	240398	0	0	0
T5	2525	1056	0	0
T6	0	791	0	0
T8	6685	5614	0	0
T12	0	1296	0	0
T14	0	113	0	0
T18	0	1801	0	0
T20	1934	0	0	0
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	0	0	0
T28	0	274	0	0
T29	2509	254	0	0
T31	1980	0	0	0
T56	0	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T86,T87
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T37
1	0	1	Covered	T3,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9688357	543776	0	0
DepthKnown_A	10084005	9907209	0	0
RvalidKnown_A	10084005	9907209	0	0
WreadyKnown_A	10084005	9907209	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	9873387	589649	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9688357	543776	0	0
T3	2400	935	0	0
T4	240398	0	0	0
T5	383	269	0	0
T6	0	54	0	0
T8	6685	5623	0	0
T12	0	1402	0	0
T18	0	1795	0	0
T20	1934	0	0	0
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	0	0	0
T28	0	274	0	0
T29	2509	267	0	0
T31	416	0	0	0
T56	0	972	0	0
T83	0	316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10084005	9907209	0	0
T1	1043	964	0	0
T2	103705	103608	0	0
T3	2400	2350	0	0
T4	240398	240287	0	0
T5	2525	2420	0	0
T8	6685	6600	0	0
T20	1934	1881	0	0
T21	1231	1158	0	0
T22	918	819	0	0
T23	3689	3620	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	9873387	589649	0	0
T3	2400	935	0	0
T4	240398	0	0	0
T5	2525	1218	0	0
T6	0	809	0	0
T8	6685	5623	0	0
T12	0	1402	0	0
T14	0	111	0	0
T18	0	1795	0	0
T20	1934	0	0	0
T21	1231	0	0	0
T22	918	0	0	0
T23	3689	0	0	0
T28	0	274	0	0
T29	2509	267	0	0
T31	1980	0	0	0
T56	0	972	0	0