Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 98.25 93.97 97.02 92.44 96.37 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 94.23 99.92 92.75 82.54 92.44 98.83 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT21,T15,T23

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T17,T18
10CoveredT1,T4,T13

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T21,T22,T5 Yes T21,T22,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
tl_i.a_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T31,T32,T33 Yes T31,T32,T33 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
edn_i[1].edn_req Yes Yes T34,T35,T36 Yes T34,T35,T36 INPUT
edn_i[2].edn_req Yes Yes T37,T10,T19 Yes T37,T10,T19 INPUT
edn_i[3].edn_req Yes Yes T15,T37,T10 Yes T15,T37,T10 INPUT
edn_i[4].edn_req Yes Yes T10,T34,T38 Yes T10,T34,T38 INPUT
edn_i[5].edn_req Yes Yes T19,T35,T39 Yes T19,T35,T39 INPUT
edn_i[6].edn_req Yes Yes T1,T12,T40 Yes T1,T12,T40 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
edn_o[0].edn_fips Yes Yes T2,T3,T22 Yes T2,T3,T9 OUTPUT
edn_o[0].edn_ack Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T34,T35,T36 Yes T34,T35,T36 OUTPUT
edn_o[1].edn_fips Yes Yes T34,T41,T42 Yes T34,T36,T38 OUTPUT
edn_o[1].edn_ack Yes Yes T34,T35,T36 Yes T34,T35,T36 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T37,T10,T11 Yes T37,T10,T11 OUTPUT
edn_o[2].edn_fips Yes Yes T10,T11,T43 Yes T37,T10,T11 OUTPUT
edn_o[2].edn_ack Yes Yes T37,T10,T19 Yes T37,T10,T19 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T15,T37,T10 Yes T15,T37,T10 OUTPUT
edn_o[3].edn_fips Yes Yes T11,T34,T38 Yes T37,T10,T11 OUTPUT
edn_o[3].edn_ack Yes Yes T15,T37,T10 Yes T15,T37,T10 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T10,T34,T38 Yes T10,T34,T38 OUTPUT
edn_o[4].edn_fips Yes Yes T10,T38,T44 Yes T10,T38,T44 OUTPUT
edn_o[4].edn_ack Yes Yes T10,T34,T38 Yes T10,T34,T38 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T35,T38,T45 Yes T19,T35,T38 OUTPUT
edn_o[5].edn_fips Yes Yes T35,T39,T44 Yes T19,T35,T39 OUTPUT
edn_o[5].edn_ack Yes Yes T19,T35,T39 Yes T19,T35,T39 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T12,T40,T46 Yes T12,T40,T46 OUTPUT
edn_o[6].edn_fips Yes Yes T12,T46,T42 Yes T12,T46,T41 OUTPUT
edn_o[6].edn_ack Yes Yes T12,T40,T46 Yes T12,T40,T46 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T9 Yes T2,T3,T22 INPUT
csrng_cmd_i.genbits_fips Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
csrng_cmd_i.genbits_valid Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T21,T23,T47 Yes T21,T23,T47 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T21,T15,T23 Yes T21,T15,T23 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T4,T13 Yes T1,T4,T13 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T21,T15,T23 Yes T21,T15,T23 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T4,T13 Yes T1,T4,T13 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T5,T48,T49 Yes T5,T48,T49 OUTPUT
intr_edn_fatal_err_o Yes Yes T5,T43,T39 Yes T5,T43,T39 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 10995242 10801327 0 0
CsrngAppIfOut_A 10995242 10801327 0 0
FpvSecCmCntAlertCheck_A 10995242 129 0 0
FpvSecCmGenCmdFifoRptrCheck_A 10995242 90 0 0
FpvSecCmGenCmdFifoWptrCheck_A 10995242 90 0 0
FpvSecCmMainFsmCheck_A 10995242 90 0 0
FpvSecCmRegWeOnehotCheck_A 10995242 90 0 0
FpvSecCmResCmdFifoRptrCheck_A 10995242 90 0 0
FpvSecCmResCmdFifoWptrCheck_A 10995242 90 0 0
IntrEdnCmdReqDoneKnownO_A 10995242 10801327 0 0
TlAReadyKnownO_A 10995242 10801327 0 0
TlDValidKnownO_A 10995242 10801327 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 10995242 90 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 10995242 90 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 10995242 90 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 10995242 90 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 10995242 90 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 10995242 90 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 10995242 90 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 10995242 534938 0 276
gen_edn_if_asserts[0].EdnDataStable_A 10995242 23497 0 431
gen_edn_if_asserts[0].EdnEndPointOut_A 10995242 10801327 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 10995242 170702 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 10995242 534938 0 276
gen_edn_if_asserts[1].EdnDataStable_A 10995242 3555 0 125
gen_edn_if_asserts[1].EdnEndPointOut_A 10995242 10801327 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 10995242 170702 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 10995242 534938 0 276
gen_edn_if_asserts[2].EdnDataStable_A 10995242 5098 0 132
gen_edn_if_asserts[2].EdnEndPointOut_A 10995242 10801327 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 10995242 170702 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 10995242 534938 0 276
gen_edn_if_asserts[3].EdnDataStable_A 10995242 3654 0 113
gen_edn_if_asserts[3].EdnEndPointOut_A 10995242 10801327 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 10995242 170702 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 10995242 534938 0 276
gen_edn_if_asserts[4].EdnDataStable_A 10995242 3578 0 100
gen_edn_if_asserts[4].EdnEndPointOut_A 10995242 10801327 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 10995242 170702 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 10995242 534938 0 276
gen_edn_if_asserts[5].EdnDataStable_A 10995242 2854 0 92
gen_edn_if_asserts[5].EdnEndPointOut_A 10995242 10801327 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 10995242 170702 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 10995242 534938 0 276
gen_edn_if_asserts[6].EdnDataStable_A 10995242 1500 0 88
gen_edn_if_asserts[6].EdnEndPointOut_A 10995242 10801327 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 10995242 170702 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 129 0 0
T1 1808 1 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 0 0 0
T5 9181 0 0 0
T9 2279 0 0 0
T13 0 1 0 0
T14 0 1 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T50 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T54 0 1 0 0
T55 0 1 0 0
T56 0 1 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 90 0 0
T16 47000 20 0 0
T17 0 20 0 0
T18 0 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T59 1547 0 0 0
T60 1503 0 0 0
T61 1420 0 0 0
T62 1360 0 0 0
T63 980 0 0 0
T64 1376 0 0 0
T65 703 0 0 0
T66 1753 0 0 0
T67 1661 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 534938 0 276
T1 1808 1083 0 0
T2 2929 233 0 0
T3 1925 51 0 0
T4 625 196 0 0
T5 9181 1092 0 0
T9 2279 1053 0 2
T15 1968 307 0 0
T19 0 0 0 2
T20 0 0 0 2
T21 1881 221 0 0
T22 3963 82 0 0
T23 2279 237 0 0
T45 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2
T73 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 23497 0 431
T2 2929 75 0 1
T3 1925 78 0 1
T4 625 0 0 0
T5 9181 10 0 0
T9 2279 4 0 0
T10 0 0 0 1
T15 1968 0 0 0
T21 1881 4 0 1
T22 3963 23 0 1
T23 2279 8 0 1
T37 0 50 0 1
T74 1013 3 0 1
T75 0 3 0 1
T76 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 170702 0 0
T1 1808 1084 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 236 0 0
T5 9181 0 0 0
T6 0 442 0 0
T9 2279 0 0 0
T13 0 254 0 0
T14 0 1080 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T24 0 12 0 0
T39 0 610 0 0
T43 0 215 0 0
T77 0 394 0 0
T78 0 427 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 534938 0 276
T1 1808 1083 0 0
T2 2929 233 0 0
T3 1925 51 0 0
T4 625 196 0 0
T5 9181 1092 0 0
T9 2279 1053 0 2
T15 1968 307 0 0
T19 0 0 0 2
T20 0 0 0 2
T21 1881 221 0 0
T22 3963 82 0 0
T23 2279 237 0 0
T45 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2
T73 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 3555 0 125
T12 2777 0 0 0
T34 2816 34 0 1
T35 2152 4 0 1
T36 0 4 0 1
T38 0 3 0 1
T41 0 20 0 1
T42 0 26 0 1
T44 0 3 0 1
T69 1307 0 0 0
T70 823 0 0 0
T77 1781 0 0 0
T79 0 3 0 1
T80 0 4 0 1
T81 0 4 0 1
T82 1358 0 0 0
T83 2288 0 0 0
T84 1257 0 0 0
T85 2520 0 0 0

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 170702 0 0
T1 1808 1084 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 236 0 0
T5 9181 0 0 0
T6 0 442 0 0
T9 2279 0 0 0
T13 0 254 0 0
T14 0 1080 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T24 0 12 0 0
T39 0 610 0 0
T43 0 215 0 0
T77 0 394 0 0
T78 0 427 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 534938 0 276
T1 1808 1083 0 0
T2 2929 233 0 0
T3 1925 51 0 0
T4 625 196 0 0
T5 9181 1092 0 0
T9 2279 1053 0 2
T15 1968 307 0 0
T19 0 0 0 2
T20 0 0 0 2
T21 1881 221 0 0
T22 3963 82 0 0
T23 2279 237 0 0
T45 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2
T73 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 5098 0 132
T10 3609 40 0 1
T11 2712 22 0 1
T12 0 38 0 1
T13 564 0 0 0
T19 1612 1 0 0
T37 1751 3 0 1
T38 0 3 0 1
T41 0 0 0 1
T43 0 1 0 0
T44 0 0 0 1
T46 0 40 0 1
T47 1821 0 0 0
T68 1609 0 0 0
T76 1730 0 0 0
T79 0 0 0 1
T86 2395 4 0 1
T87 0 4 0 0
T88 3374 0 0 0

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 170702 0 0
T1 1808 1084 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 236 0 0
T5 9181 0 0 0
T6 0 442 0 0
T9 2279 0 0 0
T13 0 254 0 0
T14 0 1080 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T24 0 12 0 0
T39 0 610 0 0
T43 0 215 0 0
T77 0 394 0 0
T78 0 427 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 534938 0 276
T1 1808 1083 0 0
T2 2929 233 0 0
T3 1925 51 0 0
T4 625 196 0 0
T5 9181 1092 0 0
T9 2279 1053 0 2
T15 1968 307 0 0
T19 0 0 0 2
T20 0 0 0 2
T21 1881 221 0 0
T22 3963 82 0 0
T23 2279 237 0 0
T45 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2
T73 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 3654 0 113
T5 9181 0 0 0
T10 3609 3 0 1
T11 0 69 0 1
T13 564 0 0 0
T15 1968 4 0 1
T20 0 4 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T34 0 44 0 1
T37 1751 3 0 1
T38 0 842 0 1
T41 0 0 0 1
T45 0 1 0 0
T74 1013 0 0 0
T75 1141 0 0 0
T76 1730 0 0 0
T79 0 3 0 1
T87 0 4 0 1
T89 0 0 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 170702 0 0
T1 1808 1084 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 236 0 0
T5 9181 0 0 0
T6 0 442 0 0
T9 2279 0 0 0
T13 0 254 0 0
T14 0 1080 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T24 0 12 0 0
T39 0 610 0 0
T43 0 215 0 0
T77 0 394 0 0
T78 0 427 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 534938 0 276
T1 1808 1083 0 0
T2 2929 233 0 0
T3 1925 51 0 0
T4 625 196 0 0
T5 9181 1092 0 0
T9 2279 1053 0 2
T15 1968 307 0 0
T19 0 0 0 2
T20 0 0 0 2
T21 1881 221 0 0
T22 3963 82 0 0
T23 2279 237 0 0
T45 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2
T73 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 3578 0 100
T10 3609 52 0 1
T11 2712 0 0 0
T14 0 1 0 0
T19 1612 0 0 0
T34 0 3 0 1
T38 0 57 0 1
T41 0 43 0 1
T43 595 0 0 0
T44 0 48 0 1
T47 1821 0 0 0
T68 1609 0 0 0
T72 0 4 0 0
T76 1730 0 0 0
T79 0 3 0 1
T86 2395 0 0 0
T88 3374 0 0 0
T89 0 3 0 1
T90 0 3 0 1
T91 1873 0 0 0
T92 0 0 0 1
T93 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 170702 0 0
T1 1808 1084 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 236 0 0
T5 9181 0 0 0
T6 0 442 0 0
T9 2279 0 0 0
T13 0 254 0 0
T14 0 1080 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T24 0 12 0 0
T39 0 610 0 0
T43 0 215 0 0
T77 0 394 0 0
T78 0 427 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 534938 0 276
T1 1808 1083 0 0
T2 2929 233 0 0
T3 1925 51 0 0
T4 625 196 0 0
T5 9181 1092 0 0
T9 2279 1053 0 2
T15 1968 307 0 0
T19 0 0 0 2
T20 0 0 0 2
T21 1881 221 0 0
T22 3963 82 0 0
T23 2279 237 0 0
T45 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2
T73 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 2854 0 92
T11 2712 0 0 0
T12 2777 0 0 0
T19 1612 4 0 0
T28 0 1 0 0
T34 2816 0 0 0
T35 0 4 0 0
T38 0 36 0 1
T39 0 1 0 0
T41 0 10 0 1
T43 595 0 0 0
T44 0 22 0 1
T45 0 4 0 0
T79 0 3 0 1
T86 2395 0 0 0
T90 0 15 0 1
T91 1873 0 0 0
T92 0 0 0 1
T93 0 0 0 1
T94 2282 0 0 0
T95 1832 0 0 0
T96 863 0 0 0
T97 0 0 0 1
T98 0 0 0 1
T99 0 0 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 170702 0 0
T1 1808 1084 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 236 0 0
T5 9181 0 0 0
T6 0 442 0 0
T9 2279 0 0 0
T13 0 254 0 0
T14 0 1080 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T24 0 12 0 0
T39 0 610 0 0
T43 0 215 0 0
T77 0 394 0 0
T78 0 427 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 534938 0 276
T1 1808 1083 0 0
T2 2929 233 0 0
T3 1925 51 0 0
T4 625 196 0 0
T5 9181 1092 0 0
T9 2279 1053 0 2
T15 1968 307 0 0
T19 0 0 0 2
T20 0 0 0 2
T21 1881 221 0 0
T22 3963 82 0 0
T23 2279 237 0 0
T45 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2
T73 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 1500 0 88
T12 2777 31 0 1
T35 2152 0 0 0
T36 1915 0 0 0
T40 0 3 0 1
T41 0 3 0 1
T42 0 22 0 1
T46 0 288 0 1
T69 1307 0 0 0
T70 823 0 0 0
T77 1781 0 0 0
T79 0 3 0 1
T82 1358 0 0 0
T83 2288 0 0 0
T84 1257 0 0 0
T85 2520 0 0 0
T89 0 17 0 1
T90 0 3 0 1
T92 0 3 0 1
T100 0 3 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 10801327 0 0
T1 1808 1682 0 0
T2 2929 2860 0 0
T3 1925 1835 0 0
T4 625 456 0 0
T5 9181 8774 0 0
T9 2279 2202 0 0
T15 1968 1913 0 0
T21 1881 1799 0 0
T22 3963 3913 0 0
T23 2279 2209 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10995242 170702 0 0
T1 1808 1084 0 0
T2 2929 0 0 0
T3 1925 0 0 0
T4 625 236 0 0
T5 9181 0 0 0
T6 0 442 0 0
T9 2279 0 0 0
T13 0 254 0 0
T14 0 1080 0 0
T15 1968 0 0 0
T21 1881 0 0 0
T22 3963 0 0 0
T23 2279 0 0 0
T24 0 12 0 0
T39 0 610 0 0
T43 0 215 0 0
T77 0 394 0 0
T78 0 427 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%