Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11618683	407377	0	0
boot_gen_cmd_rd_A	11618683	3033	0	0
boot_ins_cmd_rd_A	11618683	3119	0	0
ctrl_rd_A	11618683	3299	0	0
err_code_test_rd_A	11618683	3316	0	0
intr_enable_rd_A	11618683	7556	0	0
max_num_reqs_between_reseeds_rd_A	11618683	4450	0	0
regwen_rd_A	11618683	4592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	407377	0	0
T31	214251	10504	0	0
T32	0	10164	0	0
T33	0	18233	0	0
T160	1695	0	0	0
T167	2479	0	0	0
T244	0	22744	0	0
T245	0	11809	0	0
T246	0	8026	0	0
T247	0	11756	0	0
T248	0	12031	0	0
T249	0	4638	0	0
T250	0	22223	0	0
T251	2316	0	0	0
T252	889	0	0	0
T253	3281	0	0	0
T254	2138	0	0	0
T255	3370	0	0	0
T256	1364	0	0	0
T257	1274	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	3033	0	0
T30	2134	0	0	0
T241	2439	0	0	0
T247	342440	341	0	0
T248	215296	0	0	0
T249	0	174	0	0
T258	0	177	0	0
T259	0	117	0	0
T260	0	525	0	0
T261	0	462	0	0
T262	0	295	0	0
T263	0	431	0	0
T264	0	11	0	0
T265	0	1	0	0
T266	1416	0	0	0
T267	5113	0	0	0
T268	1030	0	0	0
T269	1563	0	0	0
T270	1935	0	0	0
T271	1987	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	3119	0	0
T30	2134	0	0	0
T241	2439	0	0	0
T247	342440	382	0	0
T248	215296	0	0	0
T249	0	119	0	0
T258	0	176	0	0
T259	0	180	0	0
T260	0	497	0	0
T261	0	555	0	0
T262	0	239	0	0
T263	0	500	0	0
T264	0	16	0	0
T265	0	7	0	0
T266	1416	0	0	0
T267	5113	0	0	0
T268	1030	0	0	0
T269	1563	0	0	0
T270	1935	0	0	0
T271	1987	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	3299	0	0
T25	1286	0	0	0
T50	0	3	0	0
T92	2835	0	0	0
T97	1062	0	0	0
T111	0	2	0	0
T123	16256	8	0	0
T131	0	5	0	0
T179	1297	0	0	0
T187	2742	0	0	0
T196	1177	0	0	0
T247	0	358	0	0
T249	0	179	0	0
T272	0	18	0	0
T273	0	8	0	0
T274	0	3	0	0
T275	0	4	0	0
T276	4042	0	0	0
T277	2179	0	0	0
T278	2177	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	3316	0	0
T30	2134	0	0	0
T241	2439	0	0	0
T247	342440	386	0	0
T248	215296	0	0	0
T249	0	203	0	0
T258	0	292	0	0
T259	0	157	0	0
T260	0	474	0	0
T261	0	520	0	0
T262	0	252	0	0
T263	0	561	0	0
T264	0	3	0	0
T265	0	5	0	0
T266	1416	0	0	0
T267	5113	0	0	0
T268	1030	0	0	0
T269	1563	0	0	0
T270	1935	0	0	0
T271	1987	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	7556	0	0
T6	1278	0	0	0
T14	2067	0	0	0
T81	2748	0	0	0
T100	1291	0	0	0
T111	0	32	0	0
T121	8235	36	0	0
T122	4105	0	0	0
T123	0	14	0	0
T131	0	72	0	0
T132	0	14	0	0
T201	2179	0	0	0
T247	0	660	0	0
T249	0	397	0	0
T272	0	10	0	0
T279	0	57	0	0
T280	0	26	0	0
T281	2175	0	0	0
T282	2470	0	0	0
T283	2488	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	4450	0	0
T30	2134	0	0	0
T241	2439	0	0	0
T247	342440	340	0	0
T248	215296	0	0	0
T249	0	116	0	0
T258	0	247	0	0
T259	0	156	0	0
T260	0	563	0	0
T261	0	480	0	0
T262	0	225	0	0
T263	0	435	0	0
T264	0	17	0	0
T266	1416	0	0	0
T267	5113	0	0	0
T268	1030	0	0	0
T269	1563	0	0	0
T270	1935	0	0	0
T271	1987	0	0	0
T284	0	56	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11618683	4592	0	0
T30	2134	0	0	0
T241	2439	0	0	0
T247	342440	351	0	0
T248	215296	0	0	0
T249	0	166	0	0
T258	0	315	0	0
T259	0	146	0	0
T260	0	550	0	0
T261	0	469	0	0
T262	0	318	0	0
T263	0	455	0	0
T264	0	19	0	0
T266	1416	0	0	0
T267	5113	0	0	0
T268	1030	0	0	0
T269	1563	0	0	0
T270	1935	0	0	0
T271	1987	0	0	0
T284	0	75	0	0