Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.20	98.25	93.91	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.11	99.92	92.66	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T10,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T1,T3,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T24	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T5,T25,T11	Yes	T5,T25,T11	INPUT
edn_i[2].edn_req	Yes	Yes	T5,T25,T39	Yes	T5,T25,T39	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T25,T26	Yes	T3,T25,T26	INPUT
edn_i[4].edn_req	Yes	Yes	T25,T40,T41	Yes	T25,T40,T41	INPUT
edn_i[5].edn_req	Yes	Yes	T5,T25,T40	Yes	T5,T25,T40	INPUT
edn_i[6].edn_req	Yes	Yes	T40,T17,T42	Yes	T40,T17,T42	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T25,T10	Yes	T2,T9,T25	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T15,T43,T40	Yes	T2,T9,T15	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T5,T25,T11	Yes	T5,T25,T11	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T25,T40,T44	Yes	T5,T25,T11	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T5,T25,T11	Yes	T5,T25,T11	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T5,T25,T39	Yes	T5,T25,T39	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T5,T25,T39	Yes	T5,T25,T39	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T5,T25,T39	Yes	T5,T25,T39	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T25,T26,T44	Yes	T25,T26,T40	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T44,T45,T46	Yes	T44,T45,T47	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T25,T26,T40	Yes	T25,T26,T40	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T41,T45	Yes	T25,T40,T41	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T25,T45,T48	Yes	T25,T40,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T25,T40,T41	Yes	T25,T40,T41	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T5,T25,T40	Yes	T5,T25,T40	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T5,T45,T42	Yes	T5,T45,T42	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T5,T25,T40	Yes	T5,T25,T40	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T40,T42,T46	Yes	T40,T42,T46	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T42,T49,T50	Yes	T40,T42,T22	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T40,T42,T22	Yes	T40,T42,T22	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T5,T25,T15	Yes	T5,T25,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T5,T9,T25	Yes	T5,T9,T25	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T10,T26	Yes	T2,T10,T26	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T24,T10	Yes	T2,T24,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T3,T24	Yes	T1,T3,T24	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T24,T10	Yes	T2,T24,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T3,T24	Yes	T1,T3,T24	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T51,T36,T37	Yes	T51,T36,T37	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T4,T51	Yes	T1,T4,T51	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	13410140	13202448	0	0
CsrngAppIfOut_A	13410140	13202448	0	0
FpvSecCmCntAlertCheck_A	13410140	142	0	0
FpvSecCmGenCmdFifoRptrCheck_A	13410140	100	0	0
FpvSecCmGenCmdFifoWptrCheck_A	13410140	100	0	0
FpvSecCmMainFsmCheck_A	13410140	100	0	0
FpvSecCmRegWeOnehotCheck_A	13410140	100	0	0
FpvSecCmResCmdFifoRptrCheck_A	13410140	100	0	0
FpvSecCmResCmdFifoWptrCheck_A	13410140	100	0	0
IntrEdnCmdReqDoneKnownO_A	13410140	13202448	0	0
TlAReadyKnownO_A	13410140	13202448	0	0
TlDValidKnownO_A	13410140	13202448	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	13410140	100	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	13410140	100	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	13410140	100	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	13410140	100	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	13410140	100	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	13410140	100	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	13410140	100	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	13410140	622174	0	308
gen_edn_if_asserts[0].EdnDataStable_A	13410140	26514	0	437
gen_edn_if_asserts[0].EdnEndPointOut_A	13410140	13202448	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	13410140	179260	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	13410140	622174	0	308
gen_edn_if_asserts[1].EdnDataStable_A	13410140	4371	0	126
gen_edn_if_asserts[1].EdnEndPointOut_A	13410140	13202448	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	13410140	179260	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	13410140	622174	0	308
gen_edn_if_asserts[2].EdnDataStable_A	13410140	5900	0	119
gen_edn_if_asserts[2].EdnEndPointOut_A	13410140	13202448	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	13410140	179260	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	13410140	622174	0	308
gen_edn_if_asserts[3].EdnDataStable_A	13410140	2897	0	107
gen_edn_if_asserts[3].EdnEndPointOut_A	13410140	13202448	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	13410140	179260	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	13410140	622174	0	308
gen_edn_if_asserts[4].EdnDataStable_A	13410140	2075	0	93
gen_edn_if_asserts[4].EdnEndPointOut_A	13410140	13202448	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	13410140	179260	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	13410140	622174	0	308
gen_edn_if_asserts[5].EdnDataStable_A	13410140	4600	0	87
gen_edn_if_asserts[5].EdnEndPointOut_A	13410140	13202448	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	13410140	179260	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	13410140	622174	0	308
gen_edn_if_asserts[6].EdnDataStable_A	13410140	4662	0	81
gen_edn_if_asserts[6].EdnEndPointOut_A	13410140	13202448	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	13410140	179260	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	142	0	0
T6	0	1	0	0
T16	1499	1	0	0
T17	0	1	0	0
T36	348962	0	0	0
T40	2406	0	0	0
T41	909	0	0	0
T43	3593	0	0	0
T44	3368	0	0	0
T51	28073	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	1543	0	0	0
T60	1729	0	0	0
T61	3229	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	100	0	0
T18	65296	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	1226	0	0	0
T65	1520	0	0	0
T66	1277	0	0	0
T67	1114	0	0	0
T68	3306	0	0	0
T69	1063	0	0	0
T70	2320	0	0	0
T71	1199	0	0	0
T72	2595	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	622174	0	308
T1	1905	1013	0	0
T2	2052	231	0	0
T3	1811	46	0	0
T4	1189	505	0	0
T5	2279	15	0	0
T9	3016	1125	0	2
T10	2338	144	0	0
T21	0	0	0	2
T22	0	0	0	2
T24	1261	1176	0	2
T25	2486	38	0	0
T26	2601	213	0	0
T36	0	0	0	2
T37	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	26514	0	437
T1	1905	1	0	0
T2	2052	4	0	1
T3	1811	0	0	0
T4	1189	1	0	0
T5	2279	0	0	0
T9	3016	4	0	0
T10	2338	4	0	1
T15	0	245	0	1
T24	1261	0	0	0
T25	2486	3	0	1
T26	2601	0	0	0
T39	0	4	0	1
T40	0	0	0	1
T43	0	0	0	1
T59	0	0	0	1
T77	0	4	0	1
T78	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	179260	0	0
T1	1905	7	0	0
T2	2052	0	0	0
T3	1811	392	0	0
T4	1189	590	0	0
T5	2279	0	0	0
T6	0	428	0	0
T9	3016	0	0	0
T10	2338	0	0	0
T16	0	904	0	0
T17	0	1143	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T34	0	362	0	0
T79	0	1109	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	622174	0	308
T1	1905	1013	0	0
T2	2052	231	0	0
T3	1811	46	0	0
T4	1189	505	0	0
T5	2279	15	0	0
T9	3016	1125	0	2
T10	2338	144	0	0
T21	0	0	0	2
T22	0	0	0	2
T24	1261	1176	0	2
T25	2486	38	0	0
T26	2601	213	0	0
T36	0	0	0	2
T37	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	4371	0	126
T4	1189	0	0	0
T5	2279	3	0	1
T9	3016	0	0	0
T10	2338	0	0	0
T11	2010	4	0	1
T15	4685	0	0	0
T23	0	4	0	1
T25	2486	61	0	1
T26	2601	0	0	0
T32	0	1	0	0
T40	0	19	0	1
T42	0	3	0	1
T44	0	60	0	1
T45	0	35	0	1
T46	0	0	0	1
T77	2097	0	0	0
T78	1539	0	0	0
T80	0	279	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	179260	0	0
T1	1905	7	0	0
T2	2052	0	0	0
T3	1811	392	0	0
T4	1189	590	0	0
T5	2279	0	0	0
T6	0	428	0	0
T9	3016	0	0	0
T10	2338	0	0	0
T16	0	904	0	0
T17	0	1143	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T34	0	362	0	0
T79	0	1109	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	622174	0	308
T1	1905	1013	0	0
T2	2052	231	0	0
T3	1811	46	0	0
T4	1189	505	0	0
T5	2279	15	0	0
T9	3016	1125	0	2
T10	2338	144	0	0
T21	0	0	0	2
T22	0	0	0	2
T24	1261	1176	0	2
T25	2486	38	0	0
T26	2601	213	0	0
T36	0	0	0	2
T37	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	5900	0	119
T4	1189	0	0	0
T5	2279	50	0	1
T9	3016	0	0	0
T10	2338	0	0	0
T11	2010	0	0	0
T15	4685	0	0	0
T23	0	4	0	0
T25	2486	20	0	1
T26	2601	0	0	0
T39	0	4	0	0
T40	0	43	0	1
T42	0	41	0	1
T46	0	0	0	1
T47	0	7	0	1
T49	0	0	0	1
T77	2097	0	0	0
T78	1539	0	0	0
T81	0	4	0	1
T82	0	30	0	1
T83	0	4	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	179260	0	0
T1	1905	7	0	0
T2	2052	0	0	0
T3	1811	392	0	0
T4	1189	590	0	0
T5	2279	0	0	0
T6	0	428	0	0
T9	3016	0	0	0
T10	2338	0	0	0
T16	0	904	0	0
T17	0	1143	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T34	0	362	0	0
T79	0	1109	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	622174	0	308
T1	1905	1013	0	0
T2	2052	231	0	0
T3	1811	46	0	0
T4	1189	505	0	0
T5	2279	15	0	0
T9	3016	1125	0	2
T10	2338	144	0	0
T21	0	0	0	2
T22	0	0	0	2
T24	1261	1176	0	2
T25	2486	38	0	0
T26	2601	213	0	0
T36	0	0	0	2
T37	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	2897	0	107
T10	2338	0	0	0
T11	2010	0	0	0
T15	4685	0	0	0
T16	1499	0	0	0
T25	2486	3	0	1
T26	2601	4	0	1
T34	717	0	0	0
T39	1602	0	0	0
T40	0	3	0	1
T42	0	3	0	1
T44	0	54	0	1
T45	0	35	0	1
T46	0	8	0	1
T47	0	3	0	1
T77	2097	0	0	0
T78	1539	0	0	0
T84	0	3	0	1
T85	0	4	0	0
T86	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	179260	0	0
T1	1905	7	0	0
T2	2052	0	0	0
T3	1811	392	0	0
T4	1189	590	0	0
T5	2279	0	0	0
T6	0	428	0	0
T9	3016	0	0	0
T10	2338	0	0	0
T16	0	904	0	0
T17	0	1143	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T34	0	362	0	0
T79	0	1109	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	622174	0	308
T1	1905	1013	0	0
T2	2052	231	0	0
T3	1811	46	0	0
T4	1189	505	0	0
T5	2279	15	0	0
T9	3016	1125	0	2
T10	2338	144	0	0
T21	0	0	0	2
T22	0	0	0	2
T24	1261	1176	0	2
T25	2486	38	0	0
T26	2601	213	0	0
T36	0	0	0	2
T37	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	2075	0	93
T10	2338	0	0	0
T11	2010	0	0	0
T15	4685	0	0	0
T16	1499	0	0	0
T25	2486	11	0	1
T26	2601	0	0	0
T34	717	0	0	0
T39	1602	0	0	0
T40	0	3	0	1
T41	0	3	0	1
T42	0	3	0	1
T45	0	21	0	1
T46	0	3	0	1
T48	0	4	0	0
T49	0	3	0	1
T50	0	0	0	1
T77	2097	0	0	0
T78	1539	0	0	0
T86	0	23	0	1
T87	0	4	0	0
T88	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	179260	0	0
T1	1905	7	0	0
T2	2052	0	0	0
T3	1811	392	0	0
T4	1189	590	0	0
T5	2279	0	0	0
T6	0	428	0	0
T9	3016	0	0	0
T10	2338	0	0	0
T16	0	904	0	0
T17	0	1143	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T34	0	362	0	0
T79	0	1109	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	622174	0	308
T1	1905	1013	0	0
T2	2052	231	0	0
T3	1811	46	0	0
T4	1189	505	0	0
T5	2279	15	0	0
T9	3016	1125	0	2
T10	2338	144	0	0
T21	0	0	0	2
T22	0	0	0	2
T24	1261	1176	0	2
T25	2486	38	0	0
T26	2601	213	0	0
T36	0	0	0	2
T37	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	4600	0	87
T4	1189	0	0	0
T5	2279	7	0	1
T9	3016	0	0	0
T10	2338	0	0	0
T11	2010	0	0	0
T12	0	0	0	1
T13	0	0	0	1
T15	4685	0	0	0
T21	0	4	0	0
T25	2486	3	0	1
T26	2601	0	0	0
T40	0	4	0	1
T42	0	58	0	1
T45	0	38	0	1
T49	0	5	0	1
T77	2097	0	0	0
T78	1539	0	0	0
T88	0	3	0	1
T89	0	4	0	0
T90	0	4	0	0
T91	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	179260	0	0
T1	1905	7	0	0
T2	2052	0	0	0
T3	1811	392	0	0
T4	1189	590	0	0
T5	2279	0	0	0
T6	0	428	0	0
T9	3016	0	0	0
T10	2338	0	0	0
T16	0	904	0	0
T17	0	1143	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T34	0	362	0	0
T79	0	1109	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	622174	0	308
T1	1905	1013	0	0
T2	2052	231	0	0
T3	1811	46	0	0
T4	1189	505	0	0
T5	2279	15	0	0
T9	3016	1125	0	2
T10	2338	144	0	0
T21	0	0	0	2
T22	0	0	0	2
T24	1261	1176	0	2
T25	2486	38	0	0
T26	2601	213	0	0
T36	0	0	0	2
T37	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	4662	0	81
T22	0	1	0	0
T36	348962	0	0	0
T40	2406	3	0	1
T41	909	0	0	0
T42	0	25	0	1
T44	3368	0	0	0
T45	2921	0	0	0
T46	0	3	0	1
T49	0	35	0	1
T50	0	24	0	1
T51	28073	0	0	0
T59	1543	0	0	0
T60	1729	0	0	0
T61	3229	0	0	0
T80	0	3	0	1
T85	0	4	0	1
T88	0	387	0	1
T91	0	0	0	1
T92	0	3	0	1
T93	1559	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	179260	0	0
T1	1905	7	0	0
T2	2052	0	0	0
T3	1811	392	0	0
T4	1189	590	0	0
T5	2279	0	0	0
T6	0	428	0	0
T9	3016	0	0	0
T10	2338	0	0	0
T16	0	904	0	0
T17	0	1143	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T34	0	362	0	0
T79	0	1109	0	0