Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13896097	510919	0	0
boot_gen_cmd_rd_A	13896097	4122	0	0
boot_ins_cmd_rd_A	13896097	4441	0	0
ctrl_rd_A	13896097	4290	0	0
err_code_test_rd_A	13896097	4538	0	0
intr_enable_rd_A	13896097	9070	0	0
max_num_reqs_between_reseeds_rd_A	13896097	4514	0	0
regwen_rd_A	13896097	4992	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	510919	0	0
T23	2279	0	0	0
T29	1794	0	0	0
T36	348962	22046	0	0
T37	364082	16686	0	0
T38	0	16291	0	0
T41	909	0	0	0
T45	2921	0	0	0
T84	2534	0	0	0
T93	1559	0	0	0
T95	2600	0	0	0
T110	0	7575	0	0
T214	0	8162	0	0
T222	0	2597	0	0
T223	0	19013	0	0
T224	0	14690	0	0
T225	0	27869	0	0
T226	0	28503	0	0
T227	3863	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	4122	0	0
T30	881	0	0	0
T38	493906	527	0	0
T92	2510	0	0	0
T110	0	312	0	0
T114	2132	0	0	0
T154	2928	0	0	0
T162	718	0	0	0
T196	1768	0	0	0
T214	204309	163	0	0
T222	0	73	0	0
T224	0	394	0	0
T228	0	250	0	0
T229	0	283	0	0
T230	0	678	0	0
T231	0	117	0	0
T232	0	395	0	0
T233	1883	0	0	0
T234	3626	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	4441	0	0
T30	881	0	0	0
T38	493906	527	0	0
T92	2510	0	0	0
T110	0	293	0	0
T114	2132	0	0	0
T154	2928	0	0	0
T162	718	0	0	0
T196	1768	0	0	0
T214	204309	157	0	0
T222	0	76	0	0
T224	0	464	0	0
T228	0	301	0	0
T229	0	308	0	0
T230	0	729	0	0
T231	0	173	0	0
T232	0	423	0	0
T233	1883	0	0	0
T234	3626	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	4290	0	0
T30	881	0	0	0
T38	493906	522	0	0
T92	2510	0	0	0
T103	0	5	0	0
T110	0	285	0	0
T114	2132	0	0	0
T154	2928	0	0	0
T162	718	0	0	0
T196	1768	0	0	0
T214	204309	125	0	0
T222	0	111	0	0
T224	0	434	0	0
T228	0	246	0	0
T229	0	313	0	0
T233	1883	0	0	0
T234	3626	0	0	0
T235	0	3	0	0
T236	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	4538	0	0
T30	881	0	0	0
T38	493906	519	0	0
T92	2510	0	0	0
T110	0	318	0	0
T114	2132	0	0	0
T154	2928	0	0	0
T162	718	0	0	0
T196	1768	0	0	0
T214	204309	175	0	0
T222	0	59	0	0
T224	0	496	0	0
T228	0	269	0	0
T229	0	351	0	0
T230	0	682	0	0
T231	0	155	0	0
T232	0	504	0	0
T233	1883	0	0	0
T234	3626	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	9070	0	0
T36	348962	0	0	0
T37	364082	0	0	0
T38	0	858	0	0
T41	909	0	0	0
T44	3368	0	0	0
T45	2921	0	0	0
T51	28073	106	0	0
T61	3229	0	0	0
T73	0	6	0	0
T84	2534	0	0	0
T93	1559	0	0	0
T108	0	23	0	0
T110	0	437	0	0
T214	0	254	0	0
T222	0	152	0	0
T224	0	912	0	0
T227	3863	0	0	0
T237	0	36	0	0
T238	0	42	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	4514	0	0
T30	881	0	0	0
T38	493906	529	0	0
T92	2510	0	0	0
T110	0	303	0	0
T114	2132	0	0	0
T154	2928	0	0	0
T162	718	0	0	0
T196	1768	0	0	0
T214	204309	114	0	0
T222	0	83	0	0
T224	0	500	0	0
T228	0	276	0	0
T229	0	269	0	0
T230	0	515	0	0
T231	0	198	0	0
T232	0	394	0	0
T233	1883	0	0	0
T234	3626	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13896097	4992	0	0
T30	881	0	0	0
T38	493906	526	0	0
T92	2510	0	0	0
T110	0	205	0	0
T114	2132	0	0	0
T154	2928	0	0	0
T162	718	0	0	0
T196	1768	0	0	0
T214	204309	171	0	0
T222	0	94	0	0
T224	0	473	0	0
T228	0	253	0	0
T229	0	282	0	0
T230	0	680	0	0
T231	0	161	0	0
T232	0	483	0	0
T233	1883	0	0	0
T234	3626	0	0	0