Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.40	98.25	93.97	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.32	99.92	92.75	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T12,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T4,T5,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T17	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T10,T29	Yes	T5,T10,T29	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T17	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T17	Yes	T1,T2,T17	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T17,T5	Yes	T2,T17,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T17,T5	Yes	T2,T17,T5	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T10,T22,T40	Yes	T10,T22,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T18,T13,T19	Yes	T18,T13,T19	INPUT
edn_i[3].edn_req	Yes	Yes	T5,T29,T30	Yes	T5,T29,T30	INPUT
edn_i[4].edn_req	Yes	Yes	T24,T18,T13	Yes	T24,T18,T13	INPUT
edn_i[5].edn_req	Yes	Yes	T10,T41,T8	Yes	T10,T41,T8	INPUT
edn_i[6].edn_req	Yes	Yes	T7,T21,T42	Yes	T7,T21,T42	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T17	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T17,T6	Yes	T2,T3,T17	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T40,T13,T43	Yes	T22,T40,T13	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T43,T44,T45	Yes	T13,T43,T46	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T10,T22,T40	Yes	T10,T22,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T43,T47,T48	Yes	T13,T43,T47	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T43,T49,T34	Yes	T13,T43,T48	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T13,T43,T47	Yes	T13,T43,T47	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T29,T30,T50	Yes	T29,T30,T13	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T29,T51,T52	Yes	T29,T50,T51	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T29,T30,T13	Yes	T29,T30,T13	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T24,T23,T53	Yes	T24,T13,T23	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T44,T45,T54	Yes	T13,T23,T53	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T24,T13,T23	Yes	T24,T13,T23	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T10,T41,T13	Yes	T10,T41,T13	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T13,T43,T32	Yes	T10,T41,T13	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T10,T41,T13	Yes	T10,T41,T13	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T42,T55,T44	Yes	T21,T42,T55	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T7,T42,T56	Yes	T7,T21,T42	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T7,T21,T42	Yes	T7,T21,T42	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T17,T4	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T11,T29,T57	Yes	T3,T24,T6	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T17,T6	Yes	T6,T10,T11	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T17,T30,T58	Yes	T17,T30,T58	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T26,T12	Yes	T17,T26,T12	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T26,T12	Yes	T17,T26,T12	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T59,T60	Yes	T6,T59,T60	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T16	Yes	T4,T6,T16	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	12472250	12275519	0	0
CsrngAppIfOut_A	12472250	12275519	0	0
FpvSecCmCntAlertCheck_A	12472250	144	0	0
FpvSecCmGenCmdFifoRptrCheck_A	12472250	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	12472250	90	0	0
FpvSecCmMainFsmCheck_A	12472250	90	0	0
FpvSecCmRegWeOnehotCheck_A	12472250	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	12472250	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	12472250	90	0	0
IntrEdnCmdReqDoneKnownO_A	12472250	12275519	0	0
TlAReadyKnownO_A	12472250	12275519	0	0
TlDValidKnownO_A	12472250	12275519	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	12472250	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	12472250	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	12472250	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	12472250	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	12472250	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	12472250	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	12472250	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	12472250	595866	0	300
gen_edn_if_asserts[0].EdnDataStable_A	12472250	19145	0	398
gen_edn_if_asserts[0].EdnEndPointOut_A	12472250	12275519	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	12472250	166154	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	12472250	595866	0	300
gen_edn_if_asserts[1].EdnDataStable_A	12472250	55209	0	159
gen_edn_if_asserts[1].EdnEndPointOut_A	12472250	12275519	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	12472250	166154	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	12472250	595866	0	300
gen_edn_if_asserts[2].EdnDataStable_A	12472250	3548	0	121
gen_edn_if_asserts[2].EdnEndPointOut_A	12472250	12275519	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	12472250	166154	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	12472250	595866	0	300
gen_edn_if_asserts[3].EdnDataStable_A	12472250	2390	0	109
gen_edn_if_asserts[3].EdnEndPointOut_A	12472250	12275519	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	12472250	166154	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	12472250	595866	0	300
gen_edn_if_asserts[4].EdnDataStable_A	12472250	4451	0	90
gen_edn_if_asserts[4].EdnEndPointOut_A	12472250	12275519	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	12472250	166154	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	12472250	595866	0	300
gen_edn_if_asserts[5].EdnDataStable_A	12472250	4519	0	100
gen_edn_if_asserts[5].EdnEndPointOut_A	12472250	12275519	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	12472250	166154	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	12472250	595866	0	300
gen_edn_if_asserts[6].EdnDataStable_A	12472250	3452	0	80
gen_edn_if_asserts[6].EdnEndPointOut_A	12472250	12275519	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	12472250	166154	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	144	0	0
T5	652	1	0	0
T6	10597	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	1	0	0
T18	0	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T61	0	10	0	0
T62	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	90	0	0
T13	2075	0	0	0
T18	56368	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T23	4136	0	0	0
T50	756	0	0	0
T61	0	10	0	0
T63	0	20	0	0
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	595866	0	300
T1	1872	66	0	0
T2	1509	22	0	0
T3	2534	13	0	0
T4	1705	843	0	0
T5	652	294	0	0
T6	10597	1731	0	0
T10	0	0	0	2
T17	2262	370	0	0
T18	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	1402	96	0	0
T25	1337	28	0	0
T26	1206	1105	0	2
T55	0	0	0	2
T65	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	19145	0	398
T1	1872	3	0	1
T2	1509	3	0	1
T3	2534	22	0	1
T4	1705	1	0	0
T5	652	0	0	0
T6	10597	14	0	1
T11	0	543	0	1
T12	0	4	0	1
T17	2262	8	0	1
T24	1402	0	0	0
T25	1337	3	0	1
T26	1206	0	0	0
T27	0	3	0	1
T73	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	166154	0	0
T4	1705	18	0	0
T5	652	354	0	0
T6	10597	0	0	0
T7	0	604	0	0
T8	0	1176	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T16	0	740	0	0
T18	0	15495	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T31	0	33	0	0
T64	0	188	0	0
T74	0	1110	0	0
T75	0	402	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	595866	0	300
T1	1872	66	0	0
T2	1509	22	0	0
T3	2534	13	0	0
T4	1705	843	0	0
T5	652	294	0	0
T6	10597	1731	0	0
T10	0	0	0	2
T17	2262	370	0	0
T18	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	1402	96	0	0
T25	1337	28	0	0
T26	1206	1105	0	2
T55	0	0	0	2
T65	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	55209	0	159
T7	1215	0	0	0
T10	2468	1	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T13	0	3	0	1
T16	1463	0	0	0
T22	0	4	0	0
T27	827	0	0	0
T28	1036	0	0	0
T29	776	0	0	0
T40	0	3	0	1
T43	0	25	0	1
T46	0	3	0	1
T52	0	0	0	1
T70	1539	0	0	0
T73	1256	0	0	0
T76	0	4	0	1
T77	0	3	0	1
T78	0	3	0	1
T79	0	3	0	1
T80	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	166154	0	0
T4	1705	18	0	0
T5	652	354	0	0
T6	10597	0	0	0
T7	0	604	0	0
T8	0	1176	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T16	0	740	0	0
T18	0	15495	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T31	0	33	0	0
T64	0	188	0	0
T74	0	1110	0	0
T75	0	402	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	595866	0	300
T1	1872	66	0	0
T2	1509	22	0	0
T3	2534	13	0	0
T4	1705	843	0	0
T5	652	294	0	0
T6	10597	1731	0	0
T10	0	0	0	2
T17	2262	370	0	0
T18	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	1402	96	0	0
T25	1337	28	0	0
T26	1206	1105	0	2
T55	0	0	0	2
T65	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	3548	0	121
T13	2075	3	0	1
T23	4136	0	0	0
T43	0	51	0	1
T44	0	0	0	1
T46	0	7	0	1
T47	0	4	0	1
T48	0	4	0	0
T49	0	752	0	1
T50	756	0	0	0
T52	0	0	0	1
T64	594	0	0	0
T65	21617	0	0	0
T66	1102	0	0	0
T67	2576	0	0	0
T68	1086	0	0	0
T69	10634	0	0	0
T81	0	4	0	0
T82	0	4	0	1
T83	0	3	0	1
T84	0	4	0	0
T85	945	0	0	0
T86	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	166154	0	0
T4	1705	18	0	0
T5	652	354	0	0
T6	10597	0	0	0
T7	0	604	0	0
T8	0	1176	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T16	0	740	0	0
T18	0	15495	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T31	0	33	0	0
T64	0	188	0	0
T74	0	1110	0	0
T75	0	402	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	595866	0	300
T1	1872	66	0	0
T2	1509	22	0	0
T3	2534	13	0	0
T4	1705	843	0	0
T5	652	294	0	0
T6	10597	1731	0	0
T10	0	0	0	2
T17	2262	370	0	0
T18	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	1402	96	0	0
T25	1337	28	0	0
T26	1206	1105	0	2
T55	0	0	0	2
T65	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	2390	0	109
T7	1215	0	0	0
T12	2180	0	0	0
T13	0	3	0	1
T16	1463	0	0	0
T21	2636	0	0	0
T28	1036	0	0	0
T29	776	4	0	0
T30	0	4	0	1
T35	0	1	0	0
T44	0	0	0	1
T50	0	3	0	1
T51	0	1	0	0
T52	0	24	0	1
T54	0	0	0	1
T57	1945	0	0	0
T70	1539	0	0	0
T73	1256	0	0	0
T74	2100	0	0	0
T87	0	1	0	0
T88	0	4	0	0
T89	0	4	0	1
T90	0	0	0	1
T91	0	0	0	1
T92	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	166154	0	0
T4	1705	18	0	0
T5	652	354	0	0
T6	10597	0	0	0
T7	0	604	0	0
T8	0	1176	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T16	0	740	0	0
T18	0	15495	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T31	0	33	0	0
T64	0	188	0	0
T74	0	1110	0	0
T75	0	402	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	595866	0	300
T1	1872	66	0	0
T2	1509	22	0	0
T3	2534	13	0	0
T4	1705	843	0	0
T5	652	294	0	0
T6	10597	1731	0	0
T10	0	0	0	2
T17	2262	370	0	0
T18	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	1402	96	0	0
T25	1337	28	0	0
T26	1206	1105	0	2
T55	0	0	0	2
T65	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	4451	0	90
T6	10597	0	0	0
T7	1215	0	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T13	0	3	0	1
T23	0	4	0	0
T24	1402	3	0	1
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T44	0	29	0	1
T45	0	0	0	1
T52	0	5	0	1
T53	0	12	0	1
T54	0	0	0	1
T93	0	3	0	1
T94	0	3	0	1
T95	0	4	0	0
T96	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	166154	0	0
T4	1705	18	0	0
T5	652	354	0	0
T6	10597	0	0	0
T7	0	604	0	0
T8	0	1176	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T16	0	740	0	0
T18	0	15495	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T31	0	33	0	0
T64	0	188	0	0
T74	0	1110	0	0
T75	0	402	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	595866	0	300
T1	1872	66	0	0
T2	1509	22	0	0
T3	2534	13	0	0
T4	1705	843	0	0
T5	652	294	0	0
T6	10597	1731	0	0
T10	0	0	0	2
T17	2262	370	0	0
T18	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	1402	96	0	0
T25	1337	28	0	0
T26	1206	1105	0	2
T55	0	0	0	2
T65	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	4519	0	100
T7	1215	0	0	0
T10	2468	4	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T13	0	15	0	1
T16	1463	0	0	0
T27	827	0	0	0
T28	1036	0	0	0
T29	776	0	0	0
T32	0	1	0	0
T41	0	3	0	1
T43	0	15	0	1
T44	0	0	0	1
T52	0	60	0	1
T70	1539	0	0	0
T73	1256	0	0	0
T97	0	4	0	0
T98	0	3	0	1
T99	0	3	0	1
T100	0	4	0	1
T101	0	0	0	1
T102	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	166154	0	0
T4	1705	18	0	0
T5	652	354	0	0
T6	10597	0	0	0
T7	0	604	0	0
T8	0	1176	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T16	0	740	0	0
T18	0	15495	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T31	0	33	0	0
T64	0	188	0	0
T74	0	1110	0	0
T75	0	402	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	595866	0	300
T1	1872	66	0	0
T2	1509	22	0	0
T3	2534	13	0	0
T4	1705	843	0	0
T5	652	294	0	0
T6	10597	1731	0	0
T10	0	0	0	2
T17	2262	370	0	0
T18	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T24	1402	96	0	0
T25	1337	28	0	0
T26	1206	1105	0	2
T55	0	0	0	2
T65	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	3452	0	80
T7	1215	1	0	0
T13	0	3	0	1
T16	1463	0	0	0
T21	2636	4	0	0
T28	1036	0	0	0
T42	0	4	0	0
T43	0	3	0	1
T44	0	3	0	1
T52	0	3	0	1
T55	0	4	0	0
T57	1945	0	0	0
T59	15680	0	0	0
T70	1539	0	0	0
T71	891	0	0	0
T73	1256	0	0	0
T74	2100	0	0	0
T84	0	1	0	0
T91	0	0	0	1
T103	0	4	0	0
T104	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	166154	0	0
T4	1705	18	0	0
T5	652	354	0	0
T6	10597	0	0	0
T7	0	604	0	0
T8	0	1176	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T16	0	740	0	0
T18	0	15495	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T31	0	33	0	0
T64	0	188	0	0
T74	0	1110	0	0
T75	0	402	0	0