Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12981681	438497	0	0
boot_gen_cmd_rd_A	12981681	3941	0	0
boot_ins_cmd_rd_A	12981681	3788	0	0
ctrl_rd_A	12981681	3779	0	0
err_code_test_rd_A	12981681	3952	0	0
intr_enable_rd_A	12981681	7780	0	0
max_num_reqs_between_reseeds_rd_A	12981681	4142	0	0
regwen_rd_A	12981681	4624	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	438497	0	0
T37	170365	6137	0	0
T38	0	9196	0	0
T39	0	6263	0	0
T96	2077	0	0	0
T120	2100	0	0	0
T138	1103	0	0	0
T164	1932	0	0	0
T214	0	11266	0	0
T233	1122	0	0	0
T234	0	9982	0	0
T235	0	2783	0	0
T236	0	10984	0	0
T237	0	10669	0	0
T238	0	14325	0	0
T239	0	17174	0	0
T240	1235	0	0	0
T241	10117	0	0	0
T242	764	0	0	0
T243	1604	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	3941	0	0
T37	170365	79	0	0
T38	0	422	0	0
T96	2077	0	0	0
T120	2100	0	0	0
T138	1103	0	0	0
T164	1932	0	0	0
T233	1122	0	0	0
T235	0	96	0	0
T237	0	311	0	0
T240	1235	0	0	0
T241	10117	0	0	0
T242	764	0	0	0
T243	1604	0	0	0
T244	0	314	0	0
T245	0	57	0	0
T246	0	244	0	0
T247	0	145	0	0
T248	0	607	0	0
T249	0	559	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	3788	0	0
T37	170365	149	0	0
T38	0	290	0	0
T96	2077	0	0	0
T120	2100	0	0	0
T138	1103	0	0	0
T164	1932	0	0	0
T233	1122	0	0	0
T235	0	72	0	0
T237	0	348	0	0
T240	1235	0	0	0
T241	10117	0	0	0
T242	764	0	0	0
T243	1604	0	0	0
T244	0	278	0	0
T245	0	57	0	0
T246	0	226	0	0
T247	0	141	0	0
T248	0	548	0	0
T249	0	665	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	3779	0	0
T1	1872	10	0	0
T2	1509	0	0	0
T3	2534	0	0	0
T4	1705	0	0	0
T5	652	0	0	0
T6	10597	0	0	0
T17	2262	0	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T37	0	161	0	0
T38	0	287	0	0
T82	0	3	0	0
T116	0	24	0	0
T121	0	6	0	0
T122	0	1	0	0
T147	0	1	0	0
T216	0	7	0	0
T250	0	10	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	3952	0	0
T37	170365	127	0	0
T38	0	329	0	0
T96	2077	0	0	0
T120	2100	0	0	0
T138	1103	0	0	0
T164	1932	0	0	0
T233	1122	0	0	0
T235	0	112	0	0
T237	0	322	0	0
T240	1235	0	0	0
T241	10117	0	0	0
T242	764	0	0	0
T243	1604	0	0	0
T244	0	393	0	0
T245	0	87	0	0
T246	0	273	0	0
T247	0	169	0	0
T248	0	628	0	0
T249	0	559	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	7780	0	0
T8	2649	0	0	0
T31	1285	0	0	0
T37	0	219	0	0
T40	5043	0	0	0
T41	899	0	0	0
T55	1797	0	0	0
T60	20121	50	0	0
T72	1595	0	0	0
T109	2303	0	0	0
T116	0	4	0	0
T118	0	6	0	0
T128	0	69	0	0
T130	0	52	0	0
T241	0	9	0	0
T251	0	25	0	0
T252	0	29	0	0
T253	0	147	0	0
T254	1080	0	0	0
T255	1132	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	4142	0	0
T37	170365	103	0	0
T38	0	333	0	0
T96	2077	0	0	0
T120	2100	0	0	0
T138	1103	0	0	0
T164	1932	0	0	0
T233	1122	0	0	0
T235	0	119	0	0
T237	0	296	0	0
T240	1235	0	0	0
T241	10117	0	0	0
T242	764	0	0	0
T243	1604	0	0	0
T244	0	267	0	0
T245	0	68	0	0
T246	0	213	0	0
T247	0	92	0	0
T248	0	630	0	0
T249	0	461	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12981681	4624	0	0
T37	170365	91	0	0
T38	0	326	0	0
T96	2077	0	0	0
T120	2100	0	0	0
T138	1103	0	0	0
T164	1932	0	0	0
T233	1122	0	0	0
T235	0	110	0	0
T237	0	338	0	0
T240	1235	0	0	0
T241	10117	0	0	0
T242	764	0	0	0
T243	1604	0	0	0
T244	0	298	0	0
T245	0	110	0	0
T246	0	259	0	0
T247	0	161	0	0
T248	0	588	0	0
T249	0	589	0	0