Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.10	98.25	93.91	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.02	99.92	92.66	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T27,T18,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T20,T21
1	0	Covered	T5,T6,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T25	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T25,T27	Yes	T2,T25,T27	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T16,T11,T40	Yes	T16,T11,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T27,T5,T16	Yes	T27,T5,T16	INPUT
edn_i[3].edn_req	Yes	Yes	T16,T12,T41	Yes	T16,T12,T41	INPUT
edn_i[4].edn_req	Yes	Yes	T16,T41,T20	Yes	T16,T41,T20	INPUT
edn_i[5].edn_req	Yes	Yes	T25,T10,T6	Yes	T25,T10,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T16,T42,T41	Yes	T16,T42,T41	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T4,T29	Yes	T2,T3,T4	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T11,T41,T43	Yes	T11,T41,T43	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T11,T13,T44	Yes	T11,T43,T13	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T11,T41,T43	Yes	T11,T41,T43	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T27,T5,T45	Yes	T27,T5,T45	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T5,T46,T13	Yes	T27,T5,T30	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T27,T5,T45	Yes	T27,T5,T45	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T12,T41,T46	Yes	T12,T41,T46	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T41,T17,T46	Yes	T12,T41,T17	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T12,T41,T17	Yes	T12,T41,T17	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T41,T47,T48	Yes	T41,T47,T46	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T41,T47,T8	Yes	T41,T47,T8	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T41,T47,T46	Yes	T41,T47,T46	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T10,T22,T47	Yes	T25,T10,T22	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T22,T49,T50	Yes	T10,T12,T22	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T25,T10,T12	Yes	T25,T10,T12	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T42,T41,T13	Yes	T42,T41,T13	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T41,T49,T51	Yes	T41,T49,T52	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T42,T41,T13	Yes	T42,T41,T13	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T25	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T4,T29	Yes	T3,T4,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T29,T18	Yes	T4,T29,T42	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T26,T27,T18	Yes	T26,T27,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T26,T5,T6	Yes	T26,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T26,T27,T18	Yes	T26,T27,T18	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T26,T5,T6	Yes	T26,T5,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T31	Yes	T4,T5,T31	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	12958034	12770146	0	0
CsrngAppIfOut_A	12958034	12770146	0	0
FpvSecCmCntAlertCheck_A	12958034	123	0	0
FpvSecCmGenCmdFifoRptrCheck_A	12958034	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	12958034	80	0	0
FpvSecCmMainFsmCheck_A	12958034	80	0	0
FpvSecCmRegWeOnehotCheck_A	12958034	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	12958034	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	12958034	80	0	0
IntrEdnCmdReqDoneKnownO_A	12958034	12770146	0	0
TlAReadyKnownO_A	12958034	12770146	0	0
TlDValidKnownO_A	12958034	12770146	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	12958034	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	12958034	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	12958034	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	12958034	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	12958034	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	12958034	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	12958034	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	12958034	554353	0	298
gen_edn_if_asserts[0].EdnDataStable_A	12958034	20848	0	419
gen_edn_if_asserts[0].EdnEndPointOut_A	12958034	12770146	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	12958034	145187	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	12958034	554353	0	298
gen_edn_if_asserts[1].EdnDataStable_A	12958034	7157	0	129
gen_edn_if_asserts[1].EdnEndPointOut_A	12958034	12770146	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	12958034	145187	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	12958034	554353	0	298
gen_edn_if_asserts[2].EdnDataStable_A	12958034	4017	0	120
gen_edn_if_asserts[2].EdnEndPointOut_A	12958034	12770146	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	12958034	145187	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	12958034	554353	0	298
gen_edn_if_asserts[3].EdnDataStable_A	12958034	4378	0	115
gen_edn_if_asserts[3].EdnEndPointOut_A	12958034	12770146	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	12958034	145187	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	12958034	554353	0	298
gen_edn_if_asserts[4].EdnDataStable_A	12958034	2782	0	120
gen_edn_if_asserts[4].EdnEndPointOut_A	12958034	12770146	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	12958034	145187	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	12958034	554353	0	298
gen_edn_if_asserts[5].EdnDataStable_A	12958034	2064	0	99
gen_edn_if_asserts[5].EdnEndPointOut_A	12958034	12770146	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	12958034	145187	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	12958034	554353	0	298
gen_edn_if_asserts[6].EdnDataStable_A	12958034	3265	0	89
gen_edn_if_asserts[6].EdnEndPointOut_A	12958034	12770146	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	12958034	145187	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	123	0	0
T5	1415	1	0	0
T6	2767	0	0	0
T10	2117	0	0	0
T16	44823	20	0	0
T17	0	1	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T58	0	10	0	0
T59	0	1	0	0
T60	0	20	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	80	0	0
T16	44823	20	0	0
T18	2424	0	0	0
T19	475	0	0	0
T20	0	10	0	0
T21	0	20	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T58	0	10	0	0
T60	0	20	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T66	1352	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	554353	0	298
T1	947	11	0	0
T2	969	11	0	0
T3	3672	22	0	0
T4	10787	59	0	0
T5	1415	568	0	0
T6	2767	75	0	0
T10	2117	964	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	0	0	0	2
T20	0	0	0	2
T22	0	0	0	2
T25	1139	99	0	0
T26	1147	1061	0	2
T27	2267	129	0	0
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	20848	0	419
T1	947	3	0	1
T2	969	3	0	1
T3	3672	25	0	1
T4	10787	12	0	1
T5	1415	0	0	0
T6	2767	0	0	0
T10	2117	0	0	0
T18	0	4	0	1
T25	1139	0	0	0
T26	1147	0	0	0
T27	2267	0	0	0
T28	0	3	0	1
T29	0	29	0	1
T31	0	1	0	0
T63	0	3	0	1
T65	0	3	0	1
T69	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	145187	0	0
T5	1415	648	0	0
T6	2767	989	0	0
T10	2117	0	0	0
T16	44823	16015	0	0
T17	0	320	0	0
T19	475	202	0	0
T20	0	7236	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T40	0	1143	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T70	0	612	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	554353	0	298
T1	947	11	0	0
T2	969	11	0	0
T3	3672	22	0	0
T4	10787	59	0	0
T5	1415	568	0	0
T6	2767	75	0	0
T10	2117	964	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	0	0	0	2
T20	0	0	0	2
T22	0	0	0	2
T25	1139	99	0	0
T26	1147	1061	0	2
T27	2267	129	0	0
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	7157	0	129
T11	2886	5	0	0
T12	1882	0	0	0
T13	0	58	0	1
T30	2528	0	0	0
T32	812	0	0	0
T40	2969	0	0	0
T41	2494	3	0	1
T43	0	4	0	0
T44	0	1	0	0
T45	1057	0	0	0
T49	0	3	0	1
T51	0	0	0	1
T67	1482	0	0	0
T71	0	3	0	1
T72	0	3	0	1
T73	0	1	0	0
T74	0	4	0	0
T75	1343	0	0	0
T76	1397	0	0	0
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	145187	0	0
T5	1415	648	0	0
T6	2767	989	0	0
T10	2117	0	0	0
T16	44823	16015	0	0
T17	0	320	0	0
T19	475	202	0	0
T20	0	7236	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T40	0	1143	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T70	0	612	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	554353	0	298
T1	947	11	0	0
T2	969	11	0	0
T3	3672	22	0	0
T4	10787	59	0	0
T5	1415	568	0	0
T6	2767	75	0	0
T10	2117	964	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	0	0	0	2
T20	0	0	0	2
T22	0	0	0	2
T25	1139	99	0	0
T26	1147	1061	0	2
T27	2267	129	0	0
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	4017	0	120
T5	1415	1	0	0
T6	2767	0	0	0
T9	0	1	0	0
T10	2117	0	0	0
T13	0	15	0	1
T16	44823	0	0	0
T19	475	0	0	0
T22	0	4	0	0
T27	2267	4	0	1
T28	1030	0	0	0
T29	3883	0	0	0
T30	0	4	0	1
T41	0	3	0	1
T45	0	3	0	1
T46	0	36	0	1
T49	0	0	0	1
T63	1343	0	0	0
T64	6052	0	0	0
T71	0	3	0	1
T81	0	0	0	1
T82	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	145187	0	0
T5	1415	648	0	0
T6	2767	989	0	0
T10	2117	0	0	0
T16	44823	16015	0	0
T17	0	320	0	0
T19	475	202	0	0
T20	0	7236	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T40	0	1143	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T70	0	612	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	554353	0	298
T1	947	11	0	0
T2	969	11	0	0
T3	3672	22	0	0
T4	10787	59	0	0
T5	1415	568	0	0
T6	2767	75	0	0
T10	2117	964	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	0	0	0	2
T20	0	0	0	2
T22	0	0	0	2
T25	1139	99	0	0
T26	1147	1061	0	2
T27	2267	129	0	0
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	4378	0	115
T12	1882	4	0	0
T13	0	27	0	1
T17	746	1	0	0
T30	2528	0	0	0
T41	2494	43	0	1
T46	0	33	0	1
T56	9051	0	0	0
T70	1115	0	0	0
T71	0	24	0	1
T75	1343	0	0	0
T76	1397	0	0	0
T77	0	0	0	1
T82	0	40	0	1
T83	0	3	0	1
T84	0	4	0	1
T85	0	3	0	1
T86	1338	0	0	0
T87	2089	0	0	0
T88	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	145187	0	0
T5	1415	648	0	0
T6	2767	989	0	0
T10	2117	0	0	0
T16	44823	16015	0	0
T17	0	320	0	0
T19	475	202	0	0
T20	0	7236	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T40	0	1143	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T70	0	612	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	554353	0	298
T1	947	11	0	0
T2	969	11	0	0
T3	3672	22	0	0
T4	10787	59	0	0
T5	1415	568	0	0
T6	2767	75	0	0
T10	2117	964	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	0	0	0	2
T20	0	0	0	2
T22	0	0	0	2
T25	1139	99	0	0
T26	1147	1061	0	2
T27	2267	129	0	0
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	2782	0	120
T13	0	3	0	1
T17	746	0	0	0
T41	2494	45	0	1
T46	0	3	0	1
T47	0	4	0	0
T48	0	3	0	1
T49	0	3	0	1
T51	0	0	0	1
T56	9051	0	0	0
T57	3311	0	0	0
T70	1115	0	0	0
T75	1343	0	0	0
T76	1397	0	0	0
T77	0	21	0	1
T82	0	3	0	1
T86	1338	0	0	0
T87	2089	0	0	0
T89	0	3	0	1
T90	0	4	0	0
T91	2711	0	0	0
T92	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	145187	0	0
T5	1415	648	0	0
T6	2767	989	0	0
T10	2117	0	0	0
T16	44823	16015	0	0
T17	0	320	0	0
T19	475	202	0	0
T20	0	7236	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T40	0	1143	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T70	0	612	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	554353	0	298
T1	947	11	0	0
T2	969	11	0	0
T3	3672	22	0	0
T4	10787	59	0	0
T5	1415	568	0	0
T6	2767	75	0	0
T10	2117	964	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	0	0	0	2
T20	0	0	0	2
T22	0	0	0	2
T25	1139	99	0	0
T26	1147	1061	0	2
T27	2267	129	0	0
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	2064	0	99
T5	1415	0	0	0
T6	2767	0	0	0
T10	2117	4	0	0
T12	0	1	0	0
T16	44823	0	0	0
T22	0	4	0	0
T24	0	4	0	0
T25	1139	3	0	1
T26	1147	0	0	0
T27	2267	0	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T47	0	4	0	1
T49	0	46	0	1
T50	0	1	0	0
T51	0	0	0	1
T63	1343	0	0	0
T77	0	0	0	1
T93	0	3	0	1
T94	0	4	0	0
T95	0	0	0	1
T96	0	0	0	1
T97	0	0	0	1
T98	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	145187	0	0
T5	1415	648	0	0
T6	2767	989	0	0
T10	2117	0	0	0
T16	44823	16015	0	0
T17	0	320	0	0
T19	475	202	0	0
T20	0	7236	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T40	0	1143	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T70	0	612	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	554353	0	298
T1	947	11	0	0
T2	969	11	0	0
T3	3672	22	0	0
T4	10787	59	0	0
T5	1415	568	0	0
T6	2767	75	0	0
T10	2117	964	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	0	0	0	2
T20	0	0	0	2
T22	0	0	0	2
T25	1139	99	0	0
T26	1147	1061	0	2
T27	2267	129	0	0
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	3265	0	89
T11	2886	0	0	0
T13	0	13	0	1
T18	2424	0	0	0
T32	812	0	0	0
T40	2969	0	0	0
T41	0	56	0	1
T42	1116	4	0	0
T45	1057	0	0	0
T49	0	7	0	1
T51	0	0	0	1
T52	0	3	0	1
T66	1352	0	0	0
T67	1482	0	0	0
T69	1633	0	0	0
T77	0	3	0	1
T96	0	0	0	1
T99	0	3	0	1
T100	0	4	0	1
T101	0	1	0	0
T102	0	4	0	0
T103	1710	0	0	0
T104	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	12770146	0	0
T1	947	848	0	0
T2	969	878	0	0
T3	3672	3620	0	0
T4	10787	10446	0	0
T5	1415	1287	0	0
T6	2767	2611	0	0
T10	2117	2063	0	0
T25	1139	1059	0	0
T26	1147	1063	0	0
T27	2267	2193	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12958034	145187	0	0
T5	1415	648	0	0
T6	2767	989	0	0
T10	2117	0	0	0
T16	44823	16015	0	0
T17	0	320	0	0
T19	475	202	0	0
T20	0	7236	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T40	0	1143	0	0
T63	1343	0	0	0
T64	6052	0	0	0
T65	1106	0	0	0
T70	0	612	0	0