Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13484328	511663	0	0
boot_gen_cmd_rd_A	13484328	3217	0	0
boot_ins_cmd_rd_A	13484328	3785	0	0
ctrl_rd_A	13484328	3527	0	0
err_code_test_rd_A	13484328	3729	0	0
intr_enable_rd_A	13484328	8285	0	0
max_num_reqs_between_reseeds_rd_A	13484328	4319	0	0
regwen_rd_A	13484328	4857	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	511663	0	0
T37	88621	4212	0	0
T38	0	1621	0	0
T39	0	12653	0	0
T62	813	0	0	0
T77	3326	0	0	0
T90	873	0	0	0
T117	32908	0	0	0
T128	1990	0	0	0
T140	1617	0	0	0
T235	0	16889	0	0
T236	0	12209	0	0
T237	0	10391	0	0
T238	0	6836	0	0
T239	0	16341	0	0
T240	0	4180	0	0
T241	0	7450	0	0
T242	2198	0	0	0
T243	1037	0	0	0
T244	998	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	3217	0	0
T156	2859	0	0	0
T161	2047	0	0	0
T236	344253	410	0	0
T237	273037	0	0	0
T238	202798	153	0	0
T239	297923	0	0	0
T245	0	164	0	0
T246	0	518	0	0
T247	0	318	0	0
T248	0	485	0	0
T249	0	610	0	0
T250	0	184	0	0
T251	0	40	0	0
T252	0	4	0	0
T253	1699	0	0	0
T254	762	0	0	0
T255	2007	0	0	0
T256	30029	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	3785	0	0
T156	2859	0	0	0
T161	2047	0	0	0
T236	344253	486	0	0
T237	273037	0	0	0
T238	202798	148	0	0
T239	297923	0	0	0
T245	0	242	0	0
T246	0	566	0	0
T247	0	334	0	0
T248	0	645	0	0
T249	0	584	0	0
T250	0	250	0	0
T251	0	11	0	0
T252	0	35	0	0
T253	1699	0	0	0
T254	762	0	0	0
T255	2007	0	0	0
T256	30029	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	3527	0	0
T6	2767	7	0	0
T16	44823	0	0	0
T19	475	0	0	0
T23	0	7	0	0
T28	1030	0	0	0
T29	3883	0	0	0
T31	1303	0	0	0
T42	1116	0	0	0
T63	1343	0	0	0
T64	6052	8	0	0
T65	1106	0	0	0
T110	0	1	0	0
T236	0	452	0	0
T238	0	150	0	0
T256	0	6	0	0
T257	0	10	0	0
T258	0	1	0	0
T259	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	3729	0	0
T156	2859	0	0	0
T161	2047	0	0	0
T236	344253	437	0	0
T237	273037	0	0	0
T238	202798	154	0	0
T239	297923	0	0	0
T245	0	271	0	0
T246	0	650	0	0
T247	0	330	0	0
T248	0	640	0	0
T249	0	503	0	0
T250	0	283	0	0
T251	0	69	0	0
T252	0	9	0	0
T253	1699	0	0	0
T254	762	0	0	0
T255	2007	0	0	0
T256	30029	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	8285	0	0
T4	10787	72	0	0
T5	1415	0	0	0
T6	2767	0	0	0
T10	2117	0	0	0
T16	44823	0	0	0
T25	1139	0	0	0
T26	1147	0	0	0
T27	2267	0	0	0
T28	1030	0	0	0
T63	1343	0	0	0
T110	0	114	0	0
T116	0	91	0	0
T123	0	10	0	0
T125	0	38	0	0
T236	0	624	0	0
T238	0	304	0	0
T260	0	84	0	0
T261	0	76	0	0
T262	0	125	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	4319	0	0
T156	2859	0	0	0
T161	2047	0	0	0
T236	344253	330	0	0
T237	273037	0	0	0
T238	202798	158	0	0
T239	297923	0	0	0
T245	0	144	0	0
T246	0	500	0	0
T247	0	358	0	0
T248	0	526	0	0
T249	0	495	0	0
T250	0	226	0	0
T251	0	54	0	0
T253	1699	0	0	0
T254	762	0	0	0
T255	2007	0	0	0
T256	30029	0	0	0
T263	0	36	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13484328	4857	0	0
T156	2859	0	0	0
T161	2047	0	0	0
T236	344253	465	0	0
T237	273037	0	0	0
T238	202798	159	0	0
T239	297923	0	0	0
T245	0	285	0	0
T246	0	669	0	0
T247	0	352	0	0
T248	0	607	0	0
T249	0	528	0	0
T250	0	221	0	0
T251	0	55	0	0
T253	1699	0	0	0
T254	762	0	0	0
T255	2007	0	0	0
T256	30029	0	0	0
T263	0	63	0	0