Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.39 98.25 93.91 97.02 93.02 96.37 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 94.31 99.92 92.66 82.54 93.02 98.83 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT24,T28,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T18,T19
10CoveredT4,T5,T16

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T24,T38 Yes T1,T24,T38 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T39,T40,T41 Yes T39,T40,T41 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T7,T4 Yes T2,T3,T7 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T3,*T7 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
edn_i[1].edn_req Yes Yes T2,T7,T16 Yes T2,T7,T16 INPUT
edn_i[2].edn_req Yes Yes T7,T16,T30 Yes T7,T16,T30 INPUT
edn_i[3].edn_req Yes Yes T16,T30,T20 Yes T16,T30,T20 INPUT
edn_i[4].edn_req Yes Yes T4,T16,T42 Yes T4,T16,T42 INPUT
edn_i[5].edn_req Yes Yes T5,T16,T30 Yes T5,T16,T30 INPUT
edn_i[6].edn_req Yes Yes T1,T16,T26 Yes T1,T16,T26 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T3,T7,T24 Yes T2,T3,T7 OUTPUT
edn_o[0].edn_fips Yes Yes T6,T28,T43 Yes T6,T44,T28 OUTPUT
edn_o[0].edn_ack Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T7,T30,T45 Yes T7,T30,T45 OUTPUT
edn_o[1].edn_fips Yes Yes T7,T45,T23 Yes T7,T45,T46 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T7,T30 Yes T2,T7,T30 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T7,T30,T47 Yes T7,T30,T47 OUTPUT
edn_o[2].edn_fips Yes Yes T7,T21,T48 Yes T7,T30,T21 OUTPUT
edn_o[2].edn_ack Yes Yes T7,T30,T47 Yes T7,T30,T47 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T30,T49,T50 Yes T30,T20,T51 OUTPUT
edn_o[3].edn_fips Yes Yes T30,T52,T53 Yes T30,T52,T51 OUTPUT
edn_o[3].edn_ack Yes Yes T30,T20,T52 Yes T30,T20,T52 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T4,T42,T51 Yes T4,T42,T51 OUTPUT
edn_o[4].edn_fips Yes Yes T51,T50,T53 Yes T51,T54,T55 OUTPUT
edn_o[4].edn_ack Yes Yes T4,T42,T51 Yes T4,T42,T51 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T30,T51,T56 Yes T30,T51,T56 OUTPUT
edn_o[5].edn_fips Yes Yes T30,T51,T23 Yes T30,T51,T23 OUTPUT
edn_o[5].edn_ack Yes Yes T30,T51,T56 Yes T30,T51,T56 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T30,T57 Yes T1,T26,T30 OUTPUT
edn_o[6].edn_fips Yes Yes T30,T58,T59 Yes T1,T30,T58 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T26,T30 Yes T1,T26,T30 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T2,T7,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T7,T11 Yes T2,T7,T11 INPUT
csrng_cmd_i.genbits_fips Yes Yes T7,T30,T12 Yes T2,T7,T6 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T24,T28,T29 Yes T24,T28,T29 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T24,T25,T60 Yes T24,T25,T60 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T4,T5,T25 Yes T4,T5,T25 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T24,T25,T60 Yes T24,T25,T60 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T4,T5,T25 Yes T4,T5,T25 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T6,T61,T62 Yes T6,T61,T62 OUTPUT
intr_edn_fatal_err_o Yes Yes T4,T6,T58 Yes T4,T6,T58 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 12059788 11893164 0 0
CsrngAppIfOut_A 12059788 11893164 0 0
FpvSecCmCntAlertCheck_A 12059788 107 0 0
FpvSecCmGenCmdFifoRptrCheck_A 12059788 60 0 0
FpvSecCmGenCmdFifoWptrCheck_A 12059788 60 0 0
FpvSecCmMainFsmCheck_A 12059788 60 0 0
FpvSecCmRegWeOnehotCheck_A 12059788 60 0 0
FpvSecCmResCmdFifoRptrCheck_A 12059788 60 0 0
FpvSecCmResCmdFifoWptrCheck_A 12059788 60 0 0
IntrEdnCmdReqDoneKnownO_A 12059788 11893164 0 0
TlAReadyKnownO_A 12059788 11893164 0 0
TlDValidKnownO_A 12059788 11893164 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 12059788 60 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 12059788 60 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 12059788 60 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 12059788 60 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 12059788 60 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 12059788 60 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 12059788 60 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 12059788 551187 0 274
gen_edn_if_asserts[0].EdnDataStable_A 12059788 73325 0 414
gen_edn_if_asserts[0].EdnEndPointOut_A 12059788 11893164 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 12059788 139636 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 12059788 551187 0 274
gen_edn_if_asserts[1].EdnDataStable_A 12059788 3888 0 152
gen_edn_if_asserts[1].EdnEndPointOut_A 12059788 11893164 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 12059788 139636 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 12059788 551187 0 274
gen_edn_if_asserts[2].EdnDataStable_A 12059788 2209 0 125
gen_edn_if_asserts[2].EdnEndPointOut_A 12059788 11893164 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 12059788 139636 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 12059788 551187 0 274
gen_edn_if_asserts[3].EdnDataStable_A 12059788 2659 0 97
gen_edn_if_asserts[3].EdnEndPointOut_A 12059788 11893164 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 12059788 139636 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 12059788 551187 0 274
gen_edn_if_asserts[4].EdnDataStable_A 12059788 3199 0 104
gen_edn_if_asserts[4].EdnEndPointOut_A 12059788 11893164 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 12059788 139636 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 12059788 551187 0 274
gen_edn_if_asserts[5].EdnDataStable_A 12059788 3396 0 89
gen_edn_if_asserts[5].EdnEndPointOut_A 12059788 11893164 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 12059788 139636 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 12059788 551187 0 274
gen_edn_if_asserts[6].EdnDataStable_A 12059788 2834 0 93
gen_edn_if_asserts[6].EdnEndPointOut_A 12059788 11893164 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 12059788 139636 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 107 0 0
T5 1395 1 0 0
T6 19197 0 0 0
T11 2689 0 0 0
T16 24304 10 0 0
T17 0 1 0 0
T18 0 10 0 0
T19 0 10 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T60 1144 0 0 0
T63 0 1 0 0
T64 0 1 0 0
T65 0 10 0 0
T66 0 1 0 0
T67 0 1 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 60 0 0
T11 2689 0 0 0
T12 2924 0 0 0
T16 24304 10 0 0
T18 0 10 0 0
T19 0 10 0 0
T26 1237 0 0 0
T27 1101 0 0 0
T30 2731 0 0 0
T31 2947 0 0 0
T38 1013 0 0 0
T58 2167 0 0 0
T60 1144 0 0 0
T65 0 10 0 0
T68 0 20 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 551187 0 274
T1 1249 51 0 0
T2 5243 2048 0 2
T3 1641 30 0 0
T4 1910 1005 0 0
T5 1395 794 0 0
T6 19197 3625 0 2
T7 1924 20 0 0
T11 0 0 0 2
T12 0 0 0 2
T16 24304 11569 0 2
T24 2455 218 0 0
T25 1368 1292 0 2
T60 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 73325 0 414
T2 5243 4 0 0
T3 1641 3 0 1
T4 1910 0 0 0
T5 1395 0 0 0
T6 19197 6 0 0
T7 1924 3 0 1
T11 0 4 0 0
T16 24304 0 0 0
T24 2455 4 0 1
T25 1368 0 0 0
T26 1237 0 0 0
T27 0 3 0 1
T28 0 0 0 1
T38 0 3 0 1
T44 0 0 0 1
T72 0 1 0 0
T73 0 3 0 1
T74 0 0 0 1
T75 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 139636 0 0
T4 1910 7 0 0
T5 1395 797 0 0
T6 19197 0 0 0
T8 0 309 0 0
T11 2689 0 0 0
T16 24304 9339 0 0
T17 0 1103 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 0 1132 0 0
T38 1013 0 0 0
T58 0 1128 0 0
T60 1144 0 0 0
T63 0 350 0 0
T64 0 1140 0 0
T72 0 340 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 551187 0 274
T1 1249 51 0 0
T2 5243 2048 0 2
T3 1641 30 0 0
T4 1910 1005 0 0
T5 1395 794 0 0
T6 19197 3625 0 2
T7 1924 20 0 0
T11 0 0 0 2
T12 0 0 0 2
T16 24304 11569 0 2
T24 2455 218 0 0
T25 1368 1292 0 2
T60 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 3888 0 152
T2 5243 1 0 0
T3 1641 0 0 0
T4 1910 0 0 0
T5 1395 0 0 0
T6 19197 0 0 0
T7 1924 33 0 1
T16 24304 0 0 0
T22 0 4 0 0
T23 0 0 0 1
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T30 0 3 0 1
T32 0 1 0 0
T45 0 38 0 1
T46 0 7 0 1
T76 0 4 0 1
T77 0 3 0 1
T78 0 3 0 1
T79 0 0 0 1
T80 0 0 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 139636 0 0
T4 1910 7 0 0
T5 1395 797 0 0
T6 19197 0 0 0
T8 0 309 0 0
T11 2689 0 0 0
T16 24304 9339 0 0
T17 0 1103 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 0 1132 0 0
T38 1013 0 0 0
T58 0 1128 0 0
T60 1144 0 0 0
T63 0 350 0 0
T64 0 1140 0 0
T72 0 340 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 551187 0 274
T1 1249 51 0 0
T2 5243 2048 0 2
T3 1641 30 0 0
T4 1910 1005 0 0
T5 1395 794 0 0
T6 19197 3625 0 2
T7 1924 20 0 0
T11 0 0 0 2
T12 0 0 0 2
T16 24304 11569 0 2
T24 2455 218 0 0
T25 1368 1292 0 2
T60 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 2209 0 125
T4 1910 0 0 0
T5 1395 0 0 0
T6 19197 0 0 0
T7 1924 20 0 1
T11 2689 0 0 0
T14 0 0 0 1
T16 24304 0 0 0
T21 0 73 0 1
T23 0 3 0 1
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T30 0 3 0 1
T47 0 4 0 0
T48 0 3 0 1
T50 0 34 0 1
T53 0 0 0 1
T60 1144 0 0 0
T81 0 4 0 0
T82 0 4 0 0
T83 0 4 0 1
T84 0 0 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 139636 0 0
T4 1910 7 0 0
T5 1395 797 0 0
T6 19197 0 0 0
T8 0 309 0 0
T11 2689 0 0 0
T16 24304 9339 0 0
T17 0 1103 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 0 1132 0 0
T38 1013 0 0 0
T58 0 1128 0 0
T60 1144 0 0 0
T63 0 350 0 0
T64 0 1140 0 0
T72 0 340 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 551187 0 274
T1 1249 51 0 0
T2 5243 2048 0 2
T3 1641 30 0 0
T4 1910 1005 0 0
T5 1395 794 0 0
T6 19197 3625 0 2
T7 1924 20 0 0
T11 0 0 0 2
T12 0 0 0 2
T16 24304 11569 0 2
T24 2455 218 0 0
T25 1368 1292 0 2
T60 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 2659 0 97
T12 2924 0 0 0
T17 1860 0 0 0
T20 0 3 0 1
T27 1101 0 0 0
T30 2731 50 0 1
T44 799 0 0 0
T49 0 4 0 0
T50 0 3 0 1
T51 0 3 0 1
T52 0 4 0 0
T53 0 23 0 1
T57 1156 0 0 0
T58 2167 0 0 0
T72 780 0 0 0
T73 982 0 0 0
T74 1452 0 0 0
T85 0 1 0 0
T86 0 4 0 0
T87 0 3 0 1
T88 0 0 0 1
T89 0 0 0 1
T90 0 0 0 1
T91 0 0 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 139636 0 0
T4 1910 7 0 0
T5 1395 797 0 0
T6 19197 0 0 0
T8 0 309 0 0
T11 2689 0 0 0
T16 24304 9339 0 0
T17 0 1103 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 0 1132 0 0
T38 1013 0 0 0
T58 0 1128 0 0
T60 1144 0 0 0
T63 0 350 0 0
T64 0 1140 0 0
T72 0 340 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 551187 0 274
T1 1249 51 0 0
T2 5243 2048 0 2
T3 1641 30 0 0
T4 1910 1005 0 0
T5 1395 794 0 0
T6 19197 3625 0 2
T7 1924 20 0 0
T11 0 0 0 2
T12 0 0 0 2
T16 24304 11569 0 2
T24 2455 218 0 0
T25 1368 1292 0 2
T60 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 3199 0 104
T4 1910 1 0 0
T5 1395 0 0 0
T6 19197 0 0 0
T11 2689 0 0 0
T16 24304 0 0 0
T23 0 13 0 1
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T38 1013 0 0 0
T42 0 3 0 1
T50 0 8 0 1
T51 0 41 0 1
T53 0 0 0 1
T54 0 3 0 1
T55 0 3 0 1
T60 1144 0 0 0
T80 0 3 0 1
T81 0 4 0 1
T92 0 4 0 0
T93 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 139636 0 0
T4 1910 7 0 0
T5 1395 797 0 0
T6 19197 0 0 0
T8 0 309 0 0
T11 2689 0 0 0
T16 24304 9339 0 0
T17 0 1103 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 0 1132 0 0
T38 1013 0 0 0
T58 0 1128 0 0
T60 1144 0 0 0
T63 0 350 0 0
T64 0 1140 0 0
T72 0 340 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 551187 0 274
T1 1249 51 0 0
T2 5243 2048 0 2
T3 1641 30 0 0
T4 1910 1005 0 0
T5 1395 794 0 0
T6 19197 3625 0 2
T7 1924 20 0 0
T11 0 0 0 2
T12 0 0 0 2
T16 24304 11569 0 2
T24 2455 218 0 0
T25 1368 1292 0 2
T60 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 3396 0 89
T12 2924 0 0 0
T14 0 3 0 1
T17 1860 0 0 0
T23 0 46 0 1
T27 1101 0 0 0
T30 2731 24 0 1
T44 799 0 0 0
T51 0 40 0 1
T53 0 38 0 1
T56 0 3 0 1
T57 1156 0 0 0
T58 2167 0 0 0
T72 780 0 0 0
T73 982 0 0 0
T74 1452 0 0 0
T88 0 0 0 1
T89 0 0 0 1
T94 0 4 0 0
T95 0 3 0 1
T96 0 4 0 1
T97 0 1 0 0

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 139636 0 0
T4 1910 7 0 0
T5 1395 797 0 0
T6 19197 0 0 0
T8 0 309 0 0
T11 2689 0 0 0
T16 24304 9339 0 0
T17 0 1103 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 0 1132 0 0
T38 1013 0 0 0
T58 0 1128 0 0
T60 1144 0 0 0
T63 0 350 0 0
T64 0 1140 0 0
T72 0 340 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 551187 0 274
T1 1249 51 0 0
T2 5243 2048 0 2
T3 1641 30 0 0
T4 1910 1005 0 0
T5 1395 794 0 0
T6 19197 3625 0 2
T7 1924 20 0 0
T11 0 0 0 2
T12 0 0 0 2
T16 24304 11569 0 2
T24 2455 218 0 0
T25 1368 1292 0 2
T60 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 2834 0 93
T1 1249 3 0 1
T2 5243 0 0 0
T3 1641 0 0 0
T4 1910 0 0 0
T5 1395 0 0 0
T6 19197 0 0 0
T7 1924 0 0 0
T12 0 4 0 0
T14 0 0 0 1
T16 24304 0 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 0 3 0 1
T30 0 18 0 1
T49 0 4 0 0
T50 0 0 0 1
T51 0 3 0 1
T53 0 0 0 1
T57 0 4 0 0
T58 0 1 0 0
T59 0 40 0 1
T88 0 0 0 1
T89 0 0 0 1
T98 0 4 0 0

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 11893164 0 0
T1 1249 1193 0 0
T2 5243 5162 0 0
T3 1641 1578 0 0
T4 1910 1790 0 0
T5 1395 1253 0 0
T6 19197 18558 0 0
T7 1924 1869 0 0
T16 24304 13552 0 0
T24 2455 2375 0 0
T25 1368 1294 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12059788 139636 0 0
T4 1910 7 0 0
T5 1395 797 0 0
T6 19197 0 0 0
T8 0 309 0 0
T11 2689 0 0 0
T16 24304 9339 0 0
T17 0 1103 0 0
T24 2455 0 0 0
T25 1368 0 0 0
T26 1237 0 0 0
T31 0 1132 0 0
T38 1013 0 0 0
T58 0 1128 0 0
T60 1144 0 0 0
T63 0 350 0 0
T64 0 1140 0 0
T72 0 340 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%