Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12536211	445945	0	0
boot_gen_cmd_rd_A	12536211	3863	0	0
boot_ins_cmd_rd_A	12536211	4440	0	0
ctrl_rd_A	12536211	3931	0	0
err_code_test_rd_A	12536211	4220	0	0
intr_enable_rd_A	12536211	8424	0	0
max_num_reqs_between_reseeds_rd_A	12536211	4735	0	0
regwen_rd_A	12536211	5208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	445945	0	0
T39	77774	2439	0	0
T40	0	8805	0	0
T41	0	18823	0	0
T150	3399	0	0	0
T228	0	16101	0	0
T240	0	14547	0	0
T241	0	14830	0	0
T242	0	7213	0	0
T243	0	3190	0	0
T244	0	4463	0	0
T245	0	17090	0	0
T246	1899	0	0	0
T247	977	0	0	0
T248	558	0	0	0
T249	12585	0	0	0
T250	24498	0	0	0
T251	1498	0	0	0
T252	945	0	0	0
T253	1563	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	3863	0	0
T40	237818	233	0	0
T172	2096	0	0	0
T195	2875	0	0	0
T225	732	0	0	0
T228	0	462	0	0
T235	1145	0	0	0
T240	0	241	0	0
T242	0	218	0	0
T244	0	192	0	0
T254	0	313	0	0
T255	0	274	0	0
T256	0	460	0	0
T257	0	265	0	0
T258	0	362	0	0
T259	1431	0	0	0
T260	1071	0	0	0
T261	700	0	0	0
T262	1188	0	0	0
T263	958	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	4440	0	0
T40	237818	287	0	0
T172	2096	0	0	0
T195	2875	0	0	0
T225	732	0	0	0
T228	0	578	0	0
T235	1145	0	0	0
T240	0	294	0	0
T242	0	220	0	0
T244	0	206	0	0
T254	0	469	0	0
T255	0	285	0	0
T256	0	457	0	0
T257	0	384	0	0
T258	0	467	0	0
T259	1431	0	0	0
T260	1071	0	0	0
T261	700	0	0	0
T262	1188	0	0	0
T263	958	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	3931	0	0
T3	1641	7	0	0
T4	1910	0	0	0
T5	1395	0	0	0
T6	19197	0	0	0
T7	1924	0	0	0
T16	24304	0	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	1	0	0
T40	0	278	0	0
T60	1144	0	0	0
T175	0	2	0	0
T222	0	3	0	0
T232	0	10	0	0
T261	0	4	0	0
T263	0	8	0	0
T264	0	7	0	0
T265	0	7	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	4220	0	0
T40	237818	251	0	0
T172	2096	0	0	0
T195	2875	0	0	0
T225	732	0	0	0
T228	0	493	0	0
T235	1145	0	0	0
T240	0	192	0	0
T242	0	302	0	0
T244	0	173	0	0
T254	0	427	0	0
T255	0	320	0	0
T256	0	520	0	0
T257	0	275	0	0
T258	0	403	0	0
T259	1431	0	0	0
T260	1071	0	0	0
T261	700	0	0	0
T262	1188	0	0	0
T263	958	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	8424	0	0
T6	19197	60	0	0
T11	2689	0	0	0
T16	24304	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T27	1101	0	0	0
T30	2731	0	0	0
T31	2947	0	0	0
T38	1013	0	0	0
T40	0	441	0	0
T60	1144	0	0	0
T61	0	73	0	0
T107	0	45	0	0
T125	0	142	0	0
T228	0	826	0	0
T250	0	90	0	0
T265	0	18	0	0
T266	0	37	0	0
T267	0	27	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	4735	0	0
T40	237818	233	0	0
T172	2096	0	0	0
T195	2875	0	0	0
T225	732	0	0	0
T228	0	490	0	0
T235	1145	0	0	0
T240	0	181	0	0
T242	0	197	0	0
T244	0	123	0	0
T254	0	395	0	0
T255	0	240	0	0
T256	0	513	0	0
T257	0	280	0	0
T258	0	444	0	0
T259	1431	0	0	0
T260	1071	0	0	0
T261	700	0	0	0
T262	1188	0	0	0
T263	958	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12536211	5208	0	0
T40	237818	298	0	0
T172	2096	0	0	0
T195	2875	0	0	0
T225	732	0	0	0
T228	0	485	0	0
T235	1145	0	0	0
T240	0	216	0	0
T242	0	267	0	0
T244	0	143	0	0
T254	0	446	0	0
T255	0	353	0	0
T256	0	481	0	0
T257	0	295	0	0
T258	0	404	0	0
T259	1431	0	0	0
T260	1071	0	0	0
T261	700	0	0	0
T262	1188	0	0	0
T263	958	0	0	0