Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11874292	400266	0	0
boot_gen_cmd_rd_A	11874292	1954	0	0
boot_ins_cmd_rd_A	11874292	2217	0	0
ctrl_rd_A	11874292	2209	0	0
err_code_test_rd_A	11874292	1976	0	0
intr_enable_rd_A	11874292	5374	0	0
max_num_reqs_between_reseeds_rd_A	11874292	2912	0	0
regwen_rd_A	11874292	3171	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	400266	0	0
T8	1003	0	0	0
T20	2621	0	0	0
T36	26231	957	0	0
T37	0	12998	0	0
T38	0	16294	0	0
T61	430	0	0	0
T105	14336	0	0	0
T116	3260	0	0	0
T226	0	15417	0	0
T227	0	14155	0	0
T228	0	13050	0	0
T229	0	7267	0	0
T230	0	7205	0	0
T231	0	12634	0	0
T232	0	10014	0	0
T233	896	0	0	0
T234	1046	0	0	0
T235	1639	0	0	0
T236	1417	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	1954	0	0
T35	1752	0	0	0
T112	2179	0	0	0
T170	946	0	0	0
T185	1243	0	0	0
T229	212514	228	0	0
T230	200695	0	0	0
T237	0	348	0	0
T238	0	180	0	0
T239	0	458	0	0
T240	0	191	0	0
T241	0	293	0	0
T242	0	36	0	0
T243	0	17	0	0
T244	0	5	0	0
T245	0	31	0	0
T246	962	0	0	0
T247	13828	0	0	0
T248	1985	0	0	0
T249	1014	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	2217	0	0
T35	1752	0	0	0
T112	2179	0	0	0
T170	946	0	0	0
T185	1243	0	0	0
T229	212514	321	0	0
T230	200695	0	0	0
T237	0	386	0	0
T238	0	266	0	0
T239	0	436	0	0
T240	0	153	0	0
T241	0	294	0	0
T242	0	76	0	0
T243	0	41	0	0
T244	0	5	0	0
T245	0	29	0	0
T246	962	0	0	0
T247	13828	0	0	0
T248	1985	0	0	0
T249	1014	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	2209	0	0
T16	24593	0	0	0
T54	775	0	0	0
T58	21970	0	0	0
T59	2204	0	0	0
T68	3717	0	0	0
T69	1159	0	0	0
T92	0	5	0	0
T115	2025	0	0	0
T116	0	3	0	0
T123	2194	0	0	0
T229	0	405	0	0
T236	0	1	0	0
T237	0	376	0	0
T250	1103	4	0	0
T251	0	2	0	0
T252	0	8	0	0
T253	0	3	0	0
T254	0	2	0	0
T255	1746	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	1976	0	0
T35	1752	0	0	0
T112	2179	0	0	0
T170	946	0	0	0
T185	1243	0	0	0
T229	212514	248	0	0
T230	200695	0	0	0
T237	0	313	0	0
T238	0	168	0	0
T239	0	491	0	0
T240	0	175	0	0
T241	0	276	0	0
T242	0	21	0	0
T243	0	56	0	0
T244	0	3	0	0
T245	0	18	0	0
T246	962	0	0	0
T247	13828	0	0	0
T248	1985	0	0	0
T249	1014	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	5374	0	0
T7	1329	0	0	0
T10	2051	0	0	0
T14	23494	0	0	0
T27	1544	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T57	9324	48	0	0
T58	0	22	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T66	0	48	0	0
T104	0	48	0	0
T229	0	416	0	0
T237	0	580	0	0
T247	0	39	0	0
T252	0	53	0	0
T256	0	53	0	0
T257	0	26	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	2912	0	0
T35	1752	0	0	0
T112	2179	0	0	0
T170	946	0	0	0
T185	1243	0	0	0
T229	212514	217	0	0
T230	200695	0	0	0
T237	0	351	0	0
T238	0	195	0	0
T239	0	525	0	0
T240	0	154	0	0
T241	0	284	0	0
T242	0	45	0	0
T243	0	39	0	0
T246	962	0	0	0
T247	13828	0	0	0
T248	1985	0	0	0
T249	1014	0	0	0
T258	0	4	0	0
T259	0	424	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11874292	3171	0	0
T35	1752	0	0	0
T112	2179	0	0	0
T170	946	0	0	0
T185	1243	0	0	0
T229	212514	314	0	0
T230	200695	0	0	0
T237	0	362	0	0
T238	0	219	0	0
T239	0	476	0	0
T240	0	202	0	0
T241	0	374	0	0
T242	0	54	0	0
T243	0	40	0	0
T244	0	10	0	0
T246	962	0	0	0
T247	13828	0	0	0
T248	1985	0	0	0
T249	1014	0	0	0
T259	0	491	0	0