Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	98.25	93.97	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.13	99.92	92.75	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T23,T10,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T5,T30

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T22	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T22,T6	Yes	T4,T22,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T4,T22	Yes	T1,T4,T22	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T22	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T23,T9	Yes	T4,T23,T9	INPUT
edn_i[2].edn_req	Yes	Yes	T39,T14,T17	Yes	T39,T14,T17	INPUT
edn_i[3].edn_req	Yes	Yes	T39,T7,T14	Yes	T39,T7,T14	INPUT
edn_i[4].edn_req	Yes	Yes	T30,T14,T40	Yes	T30,T14,T40	INPUT
edn_i[5].edn_req	Yes	Yes	T22,T14,T40	Yes	T22,T14,T40	INPUT
edn_i[6].edn_req	Yes	Yes	T39,T10,T14	Yes	T39,T10,T14	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T3,T25	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T6,T40	Yes	T1,T3,T6	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T9,T39	Yes	T23,T9,T39	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T39,T41,T42	Yes	T39,T43,T44	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T4,T23,T9	Yes	T4,T23,T9	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T39,T45,T46	Yes	T39,T17,T45	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T42,T47,T13	Yes	T39,T17,T46	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T39,T17,T45	Yes	T39,T17,T45	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T39,T40,T48	Yes	T39,T49,T40	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T39,T40,T50	Yes	T39,T49,T40	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T39,T7,T49	Yes	T39,T7,T49	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T30,T40,T51	Yes	T30,T40,T51	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T30,T52,T53	Yes	T30,T40,T52	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T30,T40,T51	Yes	T30,T40,T51	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T22,T40,T54	Yes	T22,T40,T54	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T40,T12,T55	Yes	T22,T40,T54	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T22,T40,T54	Yes	T22,T40,T54	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T39,T10,T40	Yes	T39,T10,T40	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T39,T40,T46	Yes	T39,T40,T46	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T39,T10,T40	Yes	T39,T10,T40	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T4,T22	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T22,T6	Yes	T3,T9,T6	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T23,T9	Yes	T3,T22,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T23,T56,T44	Yes	T23,T56,T44	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T23,T24,T10	Yes	T23,T24,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T24	Yes	T4,T5,T24	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T23,T24,T10	Yes	T23,T24,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T24	Yes	T4,T5,T24	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T30	Yes	T4,T6,T30	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	11370796	11194731	0	0
CsrngAppIfOut_A	11370796	11194731	0	0
FpvSecCmCntAlertCheck_A	11370796	118	0	0
FpvSecCmGenCmdFifoRptrCheck_A	11370796	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	11370796	70	0	0
FpvSecCmMainFsmCheck_A	11370796	70	0	0
FpvSecCmRegWeOnehotCheck_A	11370796	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	11370796	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	11370796	70	0	0
IntrEdnCmdReqDoneKnownO_A	11370796	11194731	0	0
TlAReadyKnownO_A	11370796	11194731	0	0
TlDValidKnownO_A	11370796	11194731	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	11370796	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	11370796	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	11370796	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	11370796	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	11370796	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	11370796	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	11370796	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	11370796	530609	0	282
gen_edn_if_asserts[0].EdnDataStable_A	11370796	119449	0	422
gen_edn_if_asserts[0].EdnEndPointOut_A	11370796	11194731	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	11370796	152439	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	11370796	530609	0	282
gen_edn_if_asserts[1].EdnDataStable_A	11370796	4751	0	124
gen_edn_if_asserts[1].EdnEndPointOut_A	11370796	11194731	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	11370796	152439	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	11370796	530609	0	282
gen_edn_if_asserts[2].EdnDataStable_A	11370796	3663	0	103
gen_edn_if_asserts[2].EdnEndPointOut_A	11370796	11194731	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	11370796	152439	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	11370796	530609	0	282
gen_edn_if_asserts[3].EdnDataStable_A	11370796	4405	0	102
gen_edn_if_asserts[3].EdnEndPointOut_A	11370796	11194731	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	11370796	152439	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	11370796	530609	0	282
gen_edn_if_asserts[4].EdnDataStable_A	11370796	2355	0	89
gen_edn_if_asserts[4].EdnEndPointOut_A	11370796	11194731	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	11370796	152439	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	11370796	530609	0	282
gen_edn_if_asserts[5].EdnDataStable_A	11370796	2179	0	78
gen_edn_if_asserts[5].EdnEndPointOut_A	11370796	11194731	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	11370796	152439	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	11370796	530609	0	282
gen_edn_if_asserts[6].EdnDataStable_A	11370796	1884	0	84
gen_edn_if_asserts[6].EdnEndPointOut_A	11370796	11194731	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	11370796	152439	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	118	0	0
T5	941	1	0	0
T6	23340	0	0	0
T7	0	1	0	0
T9	2556	0	0	0
T14	0	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T30	991	0	0	0
T39	3478	0	0	0
T52	0	1	0	0
T59	0	1	0	0
T60	0	20	0	0
T61	0	1	0	0
T62	849	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	70	0	0
T14	23494	10	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	0	20	0	0
T27	1544	0	0	0
T28	2624	0	0	0
T29	1777	0	0	0
T40	3379	0	0	0
T49	3098	0	0	0
T60	0	20	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T65	658	0	0	0
T66	16649	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	530609	0	282
T1	939	12	0	0
T2	1178	23	0	0
T3	4104	32	0	0
T4	624	174	0	0
T5	941	435	0	0
T9	2556	1266	0	2
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T22	1032	77	0	0
T23	2164	136	0	0
T24	879	798	0	2
T25	1927	14	0	0
T49	0	0	0	2
T63	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	119449	0	422
T1	939	3	0	1
T2	1178	3	0	1
T3	4104	25	0	1
T4	624	0	0	0
T5	941	1	0	0
T6	0	13	0	1
T9	2556	0	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	3	0	1
T26	0	3	0	1
T27	0	3	0	1
T40	0	0	0	1
T57	0	11	0	1
T64	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	152439	0	0
T4	624	260	0	0
T5	941	394	0	0
T6	23340	0	0	0
T7	0	604	0	0
T9	2556	0	0	0
T14	0	7724	0	0
T15	0	10500	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T29	0	7	0	0
T30	0	399	0	0
T39	3478	0	0	0
T59	0	1100	0	0
T65	0	260	0	0
T69	0	638	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	530609	0	282
T1	939	12	0	0
T2	1178	23	0	0
T3	4104	32	0	0
T4	624	174	0	0
T5	941	435	0	0
T9	2556	1266	0	2
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T22	1032	77	0	0
T23	2164	136	0	0
T24	879	798	0	2
T25	1927	14	0	0
T49	0	0	0	2
T63	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	4751	0	124
T4	624	1	0	0
T5	941	0	0	0
T6	23340	0	0	0
T9	2556	4	0	0
T11	0	0	0	1
T22	1032	0	0	0
T23	2164	4	0	1
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T28	0	4	0	1
T39	3478	27	0	1
T43	0	4	0	0
T44	0	4	0	1
T46	0	11	0	1
T62	0	3	0	1
T70	0	3	0	1
T71	0	0	0	1
T72	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	152439	0	0
T4	624	260	0	0
T5	941	394	0	0
T6	23340	0	0	0
T7	0	604	0	0
T9	2556	0	0	0
T14	0	7724	0	0
T15	0	10500	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T29	0	7	0	0
T30	0	399	0	0
T39	3478	0	0	0
T59	0	1100	0	0
T65	0	260	0	0
T69	0	638	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	530609	0	282
T1	939	12	0	0
T2	1178	23	0	0
T3	4104	32	0	0
T4	624	174	0	0
T5	941	435	0	0
T9	2556	1266	0	2
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T22	1032	77	0	0
T23	2164	136	0	0
T24	879	798	0	2
T25	1927	14	0	0
T49	0	0	0	2
T63	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	3663	0	103
T7	1329	0	0	0
T10	2051	0	0	0
T11	0	22	0	1
T12	0	0	0	1
T14	23494	0	0	0
T17	0	4	0	0
T30	991	0	0	0
T39	3478	3	0	1
T42	0	23	0	1
T45	0	4	0	0
T46	0	3	0	1
T49	3098	0	0	0
T53	0	3	0	1
T57	9324	0	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T73	0	4	0	0
T74	0	4	0	1
T75	0	3	0	1
T76	0	0	0	1
T77	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	152439	0	0
T4	624	260	0	0
T5	941	394	0	0
T6	23340	0	0	0
T7	0	604	0	0
T9	2556	0	0	0
T14	0	7724	0	0
T15	0	10500	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T29	0	7	0	0
T30	0	399	0	0
T39	3478	0	0	0
T59	0	1100	0	0
T65	0	260	0	0
T69	0	638	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	530609	0	282
T1	939	12	0	0
T2	1178	23	0	0
T3	4104	32	0	0
T4	624	174	0	0
T5	941	435	0	0
T9	2556	1266	0	2
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T22	1032	77	0	0
T23	2164	136	0	0
T24	879	798	0	2
T25	1927	14	0	0
T49	0	0	0	2
T63	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	4405	0	102
T7	1329	1	0	0
T10	2051	0	0	0
T12	0	0	0	1
T14	23494	0	0	0
T30	991	0	0	0
T39	3478	15	0	1
T40	0	43	0	1
T46	0	3	0	1
T48	0	3	0	1
T49	3098	4	0	0
T50	0	4	0	0
T55	0	0	0	1
T57	9324	0	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T68	0	4	0	0
T77	0	0	0	1
T78	0	4	0	0
T79	0	4	0	0
T80	0	0	0	1
T81	0	0	0	1
T82	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	152439	0	0
T4	624	260	0	0
T5	941	394	0	0
T6	23340	0	0	0
T7	0	604	0	0
T9	2556	0	0	0
T14	0	7724	0	0
T15	0	10500	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T29	0	7	0	0
T30	0	399	0	0
T39	3478	0	0	0
T59	0	1100	0	0
T65	0	260	0	0
T69	0	638	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	530609	0	282
T1	939	12	0	0
T2	1178	23	0	0
T3	4104	32	0	0
T4	624	174	0	0
T5	941	435	0	0
T9	2556	1266	0	2
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T22	1032	77	0	0
T23	2164	136	0	0
T24	879	798	0	2
T25	1927	14	0	0
T49	0	0	0	2
T63	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	2355	0	89
T7	1329	0	0	0
T10	2051	0	0	0
T12	0	0	0	1
T14	23494	0	0	0
T27	1544	0	0	0
T30	991	1	0	0
T40	0	3	0	1
T42	0	0	0	1
T44	0	4	0	0
T46	0	3	0	1
T49	3098	0	0	0
T51	0	3	0	1
T52	0	1	0	0
T53	0	57	0	1
T55	0	0	0	1
T57	9324	0	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T77	0	0	0	1
T83	0	3	0	1
T84	0	4	0	0
T85	0	4	0	0
T86	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	152439	0	0
T4	624	260	0	0
T5	941	394	0	0
T6	23340	0	0	0
T7	0	604	0	0
T9	2556	0	0	0
T14	0	7724	0	0
T15	0	10500	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T29	0	7	0	0
T30	0	399	0	0
T39	3478	0	0	0
T59	0	1100	0	0
T65	0	260	0	0
T69	0	638	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	530609	0	282
T1	939	12	0	0
T2	1178	23	0	0
T3	4104	32	0	0
T4	624	174	0	0
T5	941	435	0	0
T9	2556	1266	0	2
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T22	1032	77	0	0
T23	2164	136	0	0
T24	879	798	0	2
T25	1927	14	0	0
T49	0	0	0	2
T63	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	2179	0	78
T5	941	0	0	0
T6	23340	0	0	0
T9	2556	0	0	0
T11	0	0	0	1
T20	0	1	0	0
T22	1032	3	0	1
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T30	991	0	0	0
T39	3478	0	0	0
T40	0	33	0	1
T42	0	0	0	1
T46	0	3	0	1
T53	0	3	0	1
T54	0	3	0	1
T86	0	0	0	1
T87	0	3	0	1
T88	0	4	0	0
T89	0	1	0	0
T90	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	152439	0	0
T4	624	260	0	0
T5	941	394	0	0
T6	23340	0	0	0
T7	0	604	0	0
T9	2556	0	0	0
T14	0	7724	0	0
T15	0	10500	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T29	0	7	0	0
T30	0	399	0	0
T39	3478	0	0	0
T59	0	1100	0	0
T65	0	260	0	0
T69	0	638	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	530609	0	282
T1	939	12	0	0
T2	1178	23	0	0
T3	4104	32	0	0
T4	624	174	0	0
T5	941	435	0	0
T9	2556	1266	0	2
T14	0	0	0	2
T15	0	0	0	2
T16	0	0	0	2
T17	0	0	0	2
T22	1032	77	0	0
T23	2164	136	0	0
T24	879	798	0	2
T25	1927	14	0	0
T49	0	0	0	2
T63	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	1884	0	84
T7	1329	0	0	0
T10	2051	4	0	1
T11	0	0	0	1
T14	23494	0	0	0
T21	0	4	0	0
T30	991	0	0	0
T34	0	1	0	0
T39	3478	63	0	1
T40	0	56	0	1
T42	0	0	0	1
T46	0	35	0	1
T49	3098	0	0	0
T57	9324	0	0	0
T59	0	1	0	0
T62	849	0	0	0
T63	1663	0	0	0
T64	1070	0	0	0
T91	0	3	0	1
T92	0	3	0	1
T93	0	3	0	1
T94	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	11194731	0	0
T1	939	889	0	0
T2	1178	1122	0	0
T3	4104	4031	0	0
T4	624	450	0	0
T5	941	782	0	0
T9	2556	2475	0	0
T22	1032	957	0	0
T23	2164	2095	0	0
T24	879	800	0	0
T25	1927	1851	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11370796	152439	0	0
T4	624	260	0	0
T5	941	394	0	0
T6	23340	0	0	0
T7	0	604	0	0
T9	2556	0	0	0
T14	0	7724	0	0
T15	0	10500	0	0
T22	1032	0	0	0
T23	2164	0	0	0
T24	879	0	0	0
T25	1927	0	0	0
T26	1926	0	0	0
T29	0	7	0	0
T30	0	399	0	0
T39	3478	0	0	0
T59	0	1100	0	0
T65	0	260	0	0
T69	0	638	0	0