Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T5 T9 T10
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T5 T9 T10
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T5 T9 T10
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T9,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T5,T9,T10 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T31,T95,T96 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T5,T9,T10 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T29,T34,T35 |
| 1 | 0 | 1 | Covered | T5,T9,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T5,T9,T7 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T9,T10 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
22050406 |
1433069 |
0 |
0 |
| T5 |
280 |
63 |
0 |
0 |
| T6 |
46680 |
0 |
0 |
0 |
| T7 |
0 |
49 |
0 |
0 |
| T9 |
5112 |
2556 |
0 |
0 |
| T10 |
0 |
563 |
0 |
0 |
| T17 |
0 |
2409 |
0 |
0 |
| T18 |
0 |
6131 |
0 |
0 |
| T23 |
4328 |
0 |
0 |
0 |
| T24 |
1758 |
0 |
0 |
0 |
| T25 |
3854 |
0 |
0 |
0 |
| T26 |
3852 |
0 |
0 |
0 |
| T30 |
694 |
0 |
0 |
0 |
| T39 |
6956 |
0 |
0 |
0 |
| T43 |
0 |
2486 |
0 |
0 |
| T44 |
0 |
433 |
0 |
0 |
| T49 |
0 |
4189 |
0 |
0 |
| T62 |
1698 |
0 |
0 |
0 |
| T68 |
0 |
5044 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
22741592 |
22389462 |
0 |
0 |
| T1 |
1878 |
1778 |
0 |
0 |
| T2 |
2356 |
2244 |
0 |
0 |
| T3 |
8208 |
8062 |
0 |
0 |
| T4 |
1248 |
900 |
0 |
0 |
| T5 |
1882 |
1564 |
0 |
0 |
| T9 |
5112 |
4950 |
0 |
0 |
| T22 |
2064 |
1914 |
0 |
0 |
| T23 |
4328 |
4190 |
0 |
0 |
| T24 |
1758 |
1600 |
0 |
0 |
| T25 |
3854 |
3702 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
22741592 |
22389462 |
0 |
0 |
| T1 |
1878 |
1778 |
0 |
0 |
| T2 |
2356 |
2244 |
0 |
0 |
| T3 |
8208 |
8062 |
0 |
0 |
| T4 |
1248 |
900 |
0 |
0 |
| T5 |
1882 |
1564 |
0 |
0 |
| T9 |
5112 |
4950 |
0 |
0 |
| T22 |
2064 |
1914 |
0 |
0 |
| T23 |
4328 |
4190 |
0 |
0 |
| T24 |
1758 |
1600 |
0 |
0 |
| T25 |
3854 |
3702 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
22741592 |
22389462 |
0 |
0 |
| T1 |
1878 |
1778 |
0 |
0 |
| T2 |
2356 |
2244 |
0 |
0 |
| T3 |
8208 |
8062 |
0 |
0 |
| T4 |
1248 |
900 |
0 |
0 |
| T5 |
1882 |
1564 |
0 |
0 |
| T9 |
5112 |
4950 |
0 |
0 |
| T22 |
2064 |
1914 |
0 |
0 |
| T23 |
4328 |
4190 |
0 |
0 |
| T24 |
1758 |
1600 |
0 |
0 |
| T25 |
3854 |
3702 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
22416176 |
1524203 |
0 |
0 |
| T5 |
1882 |
813 |
0 |
0 |
| T6 |
46680 |
0 |
0 |
0 |
| T7 |
0 |
1129 |
0 |
0 |
| T9 |
5112 |
2556 |
0 |
0 |
| T10 |
0 |
563 |
0 |
0 |
| T17 |
0 |
2409 |
0 |
0 |
| T23 |
4328 |
0 |
0 |
0 |
| T24 |
1758 |
0 |
0 |
0 |
| T25 |
3854 |
0 |
0 |
0 |
| T26 |
3852 |
0 |
0 |
0 |
| T30 |
1982 |
0 |
0 |
0 |
| T39 |
6956 |
0 |
0 |
0 |
| T49 |
0 |
4189 |
0 |
0 |
| T62 |
1698 |
0 |
0 |
0 |
| T65 |
0 |
415 |
0 |
0 |
| T68 |
0 |
5044 |
0 |
0 |
| T69 |
0 |
282 |
0 |
0 |
| T97 |
0 |
224 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T5 T9 T10
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T5 T9 T10
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T5 T9 T10
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T45,T78 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T5,T9,T10 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T31,T95,T98 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T5,T9,T10 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T99 |
| 1 | 0 | 1 | Covered | T5,T9,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T5,T9,T7 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T9,T10 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11025203 |
710900 |
0 |
0 |
| T5 |
140 |
31 |
0 |
0 |
| T6 |
23340 |
0 |
0 |
0 |
| T7 |
0 |
19 |
0 |
0 |
| T9 |
2556 |
1269 |
0 |
0 |
| T10 |
0 |
252 |
0 |
0 |
| T17 |
0 |
1191 |
0 |
0 |
| T18 |
0 |
3059 |
0 |
0 |
| T23 |
2164 |
0 |
0 |
0 |
| T24 |
879 |
0 |
0 |
0 |
| T25 |
1927 |
0 |
0 |
0 |
| T26 |
1926 |
0 |
0 |
0 |
| T30 |
347 |
0 |
0 |
0 |
| T39 |
3478 |
0 |
0 |
0 |
| T43 |
0 |
1224 |
0 |
0 |
| T44 |
0 |
217 |
0 |
0 |
| T49 |
0 |
2078 |
0 |
0 |
| T62 |
849 |
0 |
0 |
0 |
| T68 |
0 |
2495 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
11194731 |
0 |
0 |
| T1 |
939 |
889 |
0 |
0 |
| T2 |
1178 |
1122 |
0 |
0 |
| T3 |
4104 |
4031 |
0 |
0 |
| T4 |
624 |
450 |
0 |
0 |
| T5 |
941 |
782 |
0 |
0 |
| T9 |
2556 |
2475 |
0 |
0 |
| T22 |
1032 |
957 |
0 |
0 |
| T23 |
2164 |
2095 |
0 |
0 |
| T24 |
879 |
800 |
0 |
0 |
| T25 |
1927 |
1851 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
11194731 |
0 |
0 |
| T1 |
939 |
889 |
0 |
0 |
| T2 |
1178 |
1122 |
0 |
0 |
| T3 |
4104 |
4031 |
0 |
0 |
| T4 |
624 |
450 |
0 |
0 |
| T5 |
941 |
782 |
0 |
0 |
| T9 |
2556 |
2475 |
0 |
0 |
| T22 |
1032 |
957 |
0 |
0 |
| T23 |
2164 |
2095 |
0 |
0 |
| T24 |
879 |
800 |
0 |
0 |
| T25 |
1927 |
1851 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
11194731 |
0 |
0 |
| T1 |
939 |
889 |
0 |
0 |
| T2 |
1178 |
1122 |
0 |
0 |
| T3 |
4104 |
4031 |
0 |
0 |
| T4 |
624 |
450 |
0 |
0 |
| T5 |
941 |
782 |
0 |
0 |
| T9 |
2556 |
2475 |
0 |
0 |
| T22 |
1032 |
957 |
0 |
0 |
| T23 |
2164 |
2095 |
0 |
0 |
| T24 |
879 |
800 |
0 |
0 |
| T25 |
1927 |
1851 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11208088 |
756216 |
0 |
0 |
| T5 |
941 |
397 |
0 |
0 |
| T6 |
23340 |
0 |
0 |
0 |
| T7 |
0 |
552 |
0 |
0 |
| T9 |
2556 |
1269 |
0 |
0 |
| T10 |
0 |
252 |
0 |
0 |
| T17 |
0 |
1191 |
0 |
0 |
| T23 |
2164 |
0 |
0 |
0 |
| T24 |
879 |
0 |
0 |
0 |
| T25 |
1927 |
0 |
0 |
0 |
| T26 |
1926 |
0 |
0 |
0 |
| T30 |
991 |
0 |
0 |
0 |
| T39 |
3478 |
0 |
0 |
0 |
| T49 |
0 |
2078 |
0 |
0 |
| T62 |
849 |
0 |
0 |
0 |
| T65 |
0 |
209 |
0 |
0 |
| T68 |
0 |
2495 |
0 |
0 |
| T69 |
0 |
143 |
0 |
0 |
| T97 |
0 |
113 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T5 T9 T10
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T5 T9 T10
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T5 T9 T10
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T9,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T5,T9,T10 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T96 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T5,T9,T10 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T29,T34,T35 |
| 1 | 0 | 1 | Covered | T5,T9,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T5,T9,T7 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T9,T10 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11025203 |
722169 |
0 |
0 |
| T5 |
140 |
32 |
0 |
0 |
| T6 |
23340 |
0 |
0 |
0 |
| T7 |
0 |
30 |
0 |
0 |
| T9 |
2556 |
1287 |
0 |
0 |
| T10 |
0 |
311 |
0 |
0 |
| T17 |
0 |
1218 |
0 |
0 |
| T18 |
0 |
3072 |
0 |
0 |
| T23 |
2164 |
0 |
0 |
0 |
| T24 |
879 |
0 |
0 |
0 |
| T25 |
1927 |
0 |
0 |
0 |
| T26 |
1926 |
0 |
0 |
0 |
| T30 |
347 |
0 |
0 |
0 |
| T39 |
3478 |
0 |
0 |
0 |
| T43 |
0 |
1262 |
0 |
0 |
| T44 |
0 |
216 |
0 |
0 |
| T49 |
0 |
2111 |
0 |
0 |
| T62 |
849 |
0 |
0 |
0 |
| T68 |
0 |
2549 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
11194731 |
0 |
0 |
| T1 |
939 |
889 |
0 |
0 |
| T2 |
1178 |
1122 |
0 |
0 |
| T3 |
4104 |
4031 |
0 |
0 |
| T4 |
624 |
450 |
0 |
0 |
| T5 |
941 |
782 |
0 |
0 |
| T9 |
2556 |
2475 |
0 |
0 |
| T22 |
1032 |
957 |
0 |
0 |
| T23 |
2164 |
2095 |
0 |
0 |
| T24 |
879 |
800 |
0 |
0 |
| T25 |
1927 |
1851 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
11194731 |
0 |
0 |
| T1 |
939 |
889 |
0 |
0 |
| T2 |
1178 |
1122 |
0 |
0 |
| T3 |
4104 |
4031 |
0 |
0 |
| T4 |
624 |
450 |
0 |
0 |
| T5 |
941 |
782 |
0 |
0 |
| T9 |
2556 |
2475 |
0 |
0 |
| T22 |
1032 |
957 |
0 |
0 |
| T23 |
2164 |
2095 |
0 |
0 |
| T24 |
879 |
800 |
0 |
0 |
| T25 |
1927 |
1851 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
11194731 |
0 |
0 |
| T1 |
939 |
889 |
0 |
0 |
| T2 |
1178 |
1122 |
0 |
0 |
| T3 |
4104 |
4031 |
0 |
0 |
| T4 |
624 |
450 |
0 |
0 |
| T5 |
941 |
782 |
0 |
0 |
| T9 |
2556 |
2475 |
0 |
0 |
| T22 |
1032 |
957 |
0 |
0 |
| T23 |
2164 |
2095 |
0 |
0 |
| T24 |
879 |
800 |
0 |
0 |
| T25 |
1927 |
1851 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11208088 |
767987 |
0 |
0 |
| T5 |
941 |
416 |
0 |
0 |
| T6 |
23340 |
0 |
0 |
0 |
| T7 |
0 |
577 |
0 |
0 |
| T9 |
2556 |
1287 |
0 |
0 |
| T10 |
0 |
311 |
0 |
0 |
| T17 |
0 |
1218 |
0 |
0 |
| T23 |
2164 |
0 |
0 |
0 |
| T24 |
879 |
0 |
0 |
0 |
| T25 |
1927 |
0 |
0 |
0 |
| T26 |
1926 |
0 |
0 |
0 |
| T30 |
991 |
0 |
0 |
0 |
| T39 |
3478 |
0 |
0 |
0 |
| T49 |
0 |
2111 |
0 |
0 |
| T62 |
849 |
0 |
0 |
0 |
| T65 |
0 |
206 |
0 |
0 |
| T68 |
0 |
2549 |
0 |
0 |
| T69 |
0 |
139 |
0 |
0 |
| T97 |
0 |
111 |
0 |
0 |