Line Coverage for Module :
edn_core
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 262 | 262 | 100.00 |
| ALWAYS | 223 | 40 | 40 | 100.00 |
| CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 307 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 314 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 322 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 324 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 328 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 335 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 339 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 356 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 361 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 362 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 367 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 370 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 373 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 382 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 384 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 385 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 388 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 410 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 423 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 424 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 444 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 445 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 464 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 471 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 472 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 473 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 490 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 493 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 500 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 502 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 507 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 516 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 527 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 550 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 558 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 560 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 565 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 566 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 570 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 581 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 582 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 593 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 594 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 602 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 603 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 612 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 613 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 615 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 621 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 622 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 629 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 630 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 637 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 638 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 649 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 650 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 660 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 661 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 690 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 692 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 696 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 700 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 702 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 733 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 735 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 739 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 743 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 807 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 811 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 814 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 824 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 829 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 835 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 836 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 837 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 838 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 841 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 901 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 902 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 905 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 906 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 907 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 908 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 910 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 925 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 927 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 929 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 935 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 938 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 939 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 963 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 963 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 963 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 963 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 963 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 963 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 963 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 964 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 964 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 964 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 964 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 964 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 964 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 964 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 967 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 967 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 967 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 967 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 967 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 967 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 967 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 970 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 970 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 970 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 970 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 970 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 970 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 970 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 974 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 974 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 974 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 974 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 974 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 974 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 974 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 994 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1012 | 1 | 1 | 100.00 |
222 always_ff @(posedge clk_i or negedge rst_ni)
223 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
224 1/1 cs_cmd_req_q <= '0;
Tests: T1 T2 T3
225 1/1 cs_cmd_req_vld_q <= '0;
Tests: T1 T2 T3
226 1/1 cs_cmd_req_out_q <= '0;
Tests: T1 T2 T3
227 1/1 cs_cmd_req_vld_out_q <= '0;
Tests: T1 T2 T3
228 1/1 cs_cmd_req_vld_hold_q <= '0;
Tests: T1 T2 T3
229 1/1 cmd_fifo_cnt_q <= '0;
Tests: T1 T2 T3
230 1/1 csrng_fips_q <= '0;
Tests: T1 T2 T3
231 1/1 edn_fips_q <= '0;
Tests: T1 T2 T3
232 1/1 cs_rdata_capt_q <= '0;
Tests: T1 T2 T3
233 1/1 cs_rdata_capt_vld_q <= '0;
Tests: T1 T2 T3
234 1/1 cmd_rdy_q <= '0;
Tests: T1 T2 T3
235 1/1 csrng_cmd_sts_q <= csrng_pkg::CMD_STS_SUCCESS;
Tests: T1 T2 T3
236 1/1 csrng_sw_cmd_ack_q <= '0;
Tests: T1 T2 T3
237 1/1 csrng_hw_cmd_sts_q <= csrng_pkg::CMD_STS_SUCCESS;
Tests: T1 T2 T3
238 1/1 boot_mode_q <= '0;
Tests: T1 T2 T3
239 1/1 auto_mode_q <= '0;
Tests: T1 T2 T3
240 1/1 cmd_type_q <= {1'b0, csrng_pkg::INV};
Tests: T1 T2 T3
241 1/1 cmd_reg_rdy_q <= '0;
Tests: T1 T2 T3
242 1/1 cmd_hdr_busy_q <= 1'b0;
Tests: T1 T2 T3
243 end else begin
244 1/1 cs_cmd_req_q <= cs_cmd_req_d;
Tests: T1 T2 T3
245 1/1 cs_cmd_req_vld_q <= cs_cmd_req_vld_d;
Tests: T1 T2 T3
246 1/1 cs_cmd_req_out_q <= cs_cmd_req_out_d;
Tests: T1 T2 T3
247 1/1 cs_cmd_req_vld_out_q <= cs_cmd_req_vld_out_d;
Tests: T1 T2 T3
248 1/1 cs_cmd_req_vld_hold_q <= cs_cmd_req_vld_hold_d;
Tests: T1 T2 T3
249 1/1 cmd_fifo_cnt_q <= cmd_fifo_cnt_d;
Tests: T1 T2 T3
250 1/1 csrng_fips_q <= csrng_fips_d;
Tests: T1 T2 T3
251 1/1 edn_fips_q <= edn_fips_d;
Tests: T1 T2 T3
252 1/1 cs_rdata_capt_q <= cs_rdata_capt_d;
Tests: T1 T2 T3
253 1/1 cs_rdata_capt_vld_q <= cs_rdata_capt_vld_d;
Tests: T1 T2 T3
254 1/1 cmd_rdy_q <= cmd_rdy_d;
Tests: T1 T2 T3
255 1/1 csrng_cmd_sts_q <= csrng_cmd_sts_d;
Tests: T1 T2 T3
256 1/1 csrng_sw_cmd_ack_q <= csrng_sw_cmd_ack_d;
Tests: T1 T2 T3
257 1/1 csrng_hw_cmd_ack_q <= csrng_hw_cmd_ack_d;
Tests: T1 T2 T3
258 1/1 csrng_hw_cmd_sts_q <= csrng_hw_cmd_sts_d;
Tests: T1 T2 T3
259 1/1 boot_mode_q <= boot_mode_d;
Tests: T1 T2 T3
260 1/1 auto_mode_q <= auto_mode_d;
Tests: T1 T2 T3
261 1/1 cmd_type_q <= cmd_type_d;
Tests: T1 T2 T3
262 1/1 cmd_reg_rdy_q <= cmd_reg_rdy_d;
Tests: T1 T2 T3
263 1/1 cmd_hdr_busy_q <= cmd_hdr_busy_d;
Tests: T1 T2 T3
264 end
265
266 //--------------------------------------------
267 // instantiate interrupt hardware primitives
268 //--------------------------------------------
269
270 prim_intr_hw #(
271 .Width(1)
272 ) u_intr_hw_edn_cmd_req_done (
273 .clk_i (clk_i),
274 .rst_ni (rst_ni),
275 .event_intr_i (event_edn_cmd_req_done),
276 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.edn_cmd_req_done.q),
277 .reg2hw_intr_test_q_i (reg2hw.intr_test.edn_cmd_req_done.q),
278 .reg2hw_intr_test_qe_i (reg2hw.intr_test.edn_cmd_req_done.qe),
279 .reg2hw_intr_state_q_i (reg2hw.intr_state.edn_cmd_req_done.q),
280 .hw2reg_intr_state_de_o (hw2reg.intr_state.edn_cmd_req_done.de),
281 .hw2reg_intr_state_d_o (hw2reg.intr_state.edn_cmd_req_done.d),
282 .intr_o (intr_edn_cmd_req_done_o)
283 );
284
285
286 prim_intr_hw #(
287 .Width(1)
288 ) u_intr_hw_edn_fatal_err (
289 .clk_i (clk_i),
290 .rst_ni (rst_ni),
291 .event_intr_i (event_edn_fatal_err),
292 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.edn_fatal_err.q),
293 .reg2hw_intr_test_q_i (reg2hw.intr_test.edn_fatal_err.q),
294 .reg2hw_intr_test_qe_i (reg2hw.intr_test.edn_fatal_err.qe),
295 .reg2hw_intr_state_q_i (reg2hw.intr_state.edn_fatal_err.q),
296 .hw2reg_intr_state_de_o (hw2reg.intr_state.edn_fatal_err.de),
297 .hw2reg_intr_state_d_o (hw2reg.intr_state.edn_fatal_err.d),
298 .intr_o (intr_edn_fatal_err_o)
299 );
300
301 // interrupt for sw app interface only
302 1/1 assign event_edn_cmd_req_done = csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode;
Tests: T1 T2 T3
303
304 // Counter, internal FIFO errors and FSM errors are structural errors and are always active
305 // regardless of the functional state.
306 logic fatal_loc_events;
307 1/1 assign fatal_loc_events = sfifo_rescmd_int_err ||
Tests: T1 T2 T3
308 sfifo_gencmd_int_err ||
309 edn_cntr_err_sum ||
310 edn_main_sm_err_sum ||
311 edn_ack_sm_err_sum;
312
313 // set the interrupt sources
314 1/1 assign event_edn_fatal_err = (edn_enable_fo[FatalErr] && (
Tests: T1 T2 T3
315 sfifo_rescmd_err_sum ||
316 sfifo_gencmd_err_sum )) ||
317 fatal_loc_events;
318
319 // set fifo errors that are single instances of source
320 1/1 assign sfifo_rescmd_err_sum = (|sfifo_rescmd_err) ||
Tests: T1 T2 T3
321 err_code_test_bit[0];
322 1/1 assign sfifo_gencmd_err_sum = (|sfifo_gencmd_err) ||
Tests: T1 T2 T3
323 err_code_test_bit[1];
324 1/1 assign edn_ack_sm_err_sum = (|edn_ack_sm_err) ||
Tests: T1 T2 T3
325 err_code_test_bit[20];
326 1/1 assign edn_main_sm_err_sum = edn_main_sm_err ||
Tests: T1 T2 T3
327 err_code_test_bit[21];
328 1/1 assign edn_cntr_err_sum = edn_cntr_err ||
Tests: T1 T2 T3
329 err_code_test_bit[22];
330
331 1/1 assign fifo_write_err_sum =
Tests: T1 T2 T3
332 sfifo_rescmd_err[2] ||
333 sfifo_gencmd_err[2] ||
334 err_code_test_bit[28];
335 1/1 assign fifo_read_err_sum =
Tests: T1 T2 T3
336 sfifo_rescmd_err[1] ||
337 sfifo_gencmd_err[1] ||
338 err_code_test_bit[29];
339 1/1 assign fifo_status_err_sum =
Tests: T1 T2 T3
340 sfifo_rescmd_err[0] ||
341 sfifo_gencmd_err[0] ||
342 err_code_test_bit[30];
343
344
345 // set the err code source bits
346 assign hw2reg.err_code.sfifo_rescmd_err.d = 1'b1;
347 1/1 assign hw2reg.err_code.sfifo_rescmd_err.de = edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum;
Tests: T1 T2 T3
348
349 assign hw2reg.err_code.sfifo_gencmd_err.d = 1'b1;
350 1/1 assign hw2reg.err_code.sfifo_gencmd_err.de = edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum;
Tests: T1 T2 T3
351
352 assign hw2reg.err_code.edn_ack_sm_err.d = 1'b1;
353 1/1 assign hw2reg.err_code.edn_ack_sm_err.de = edn_ack_sm_err_sum;
Tests: T1 T2 T3
354
355 assign hw2reg.err_code.edn_main_sm_err.d = 1'b1;
356 1/1 assign hw2reg.err_code.edn_main_sm_err.de = edn_main_sm_err_sum;
Tests: T1 T2 T3
357
358 assign hw2reg.err_code.edn_cntr_err.d = 1'b1;
359 1/1 assign hw2reg.err_code.edn_cntr_err.de = edn_cntr_err_sum;
Tests: T1 T2 T3
360
361 1/1 assign boot_ins_cmd = reg2hw.boot_ins_cmd.q;
Tests: T1 T2 T3
362 1/1 assign boot_gen_cmd = reg2hw.boot_gen_cmd.q;
Tests: T1 T2 T3
363
364
365 // set the err code type bits
366 assign hw2reg.err_code.fifo_write_err.d = 1'b1;
367 1/1 assign hw2reg.err_code.fifo_write_err.de = edn_enable_fo[FifoWrErr] && fifo_write_err_sum;
Tests: T1 T2 T3
368
369 assign hw2reg.err_code.fifo_read_err.d = 1'b1;
370 1/1 assign hw2reg.err_code.fifo_read_err.de = edn_enable_fo[FifoRdErr] && fifo_read_err_sum;
Tests: T1 T2 T3
371
372 assign hw2reg.err_code.fifo_state_err.d = 1'b1;
373 1/1 assign hw2reg.err_code.fifo_state_err.de = edn_enable_fo[FifoStErr] && fifo_status_err_sum;
Tests: T1 T2 T3
374
375
376 // Error forcing
377 for (genvar i = 0; i < 31; i = i+1) begin : gen_err_code_test_bit
378 31/31 assign err_code_test_bit[i] = (reg2hw.err_code_test.q == i) && reg2hw.err_code_test.qe;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
379 end : gen_err_code_test_bit
380
381 // CSRNG acknowledgement error status
382 1/1 assign csrng_ack_err = edn_enable_fo[CsrngAckErr] &&
Tests: T1 T2 T3
383 csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != csrng_pkg::CMD_STS_SUCCESS);
384 1/1 assign hw2reg.recov_alert_sts.csrng_ack_err.de = csrng_ack_err;
Tests: T23 T10 T28
385 1/1 assign hw2reg.recov_alert_sts.csrng_ack_err.d = csrng_ack_err;
Tests: T23 T10 T28
386
387 // Combine all recoverable alert signals into one singular signal.
388 1/1 assign event_edn_recov_err = edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa ||
Tests: T1 T2 T3
389 boot_req_mode_pfa || edn_enable_pfa || csrng_ack_err;
390
391 // Turn event_edn_recov_err into a pulse for the case when
392 // the signals are high for more then one cycle.
393 prim_edge_detector #(
394 .Width(1),
395 .ResetValue(0),
396 .EnSync(0)
397 ) u_prim_edge_detector_recov_alert (
398 .clk_i,
399 .rst_ni,
400 .d_i(event_edn_recov_err),
401 .q_sync_o(),
402 .q_posedge_pulse_o(recov_alert_o),
403 .q_negedge_pulse_o()
404 );
405
406 // alert - send all interrupt sources to the alert for the fatal case
407 1/1 assign fatal_alert_o = event_edn_fatal_err || sfifo_rescmd_int_err || sfifo_gencmd_int_err;
Tests: T1 T2 T3
408
409 // alert test
410 1/1 assign recov_alert_test_o = {
Tests: T1 T2 T3
411 reg2hw.alert_test.recov_alert.q &&
412 reg2hw.alert_test.recov_alert.qe
413 };
414 1/1 assign fatal_alert_test_o = {
Tests: T1 T2 T3
415 reg2hw.alert_test.fatal_alert.q &&
416 reg2hw.alert_test.fatal_alert.qe
417 };
418
419 // check for illegal enable field states, and set alert if detected
420
421 // SEC_CM: CONFIG.MUBI
422 mubi4_t mubi_edn_enable;
423 1/1 assign mubi_edn_enable = mubi4_t'(reg2hw.ctrl.edn_enable.q);
Tests: T1 T2 T3
424 1/1 assign edn_enable_pfa = mubi4_test_invalid(mubi_edn_enable_fanout[MuBiCheck]);
Tests: T1 T2 T3
425 1/1 assign hw2reg.recov_alert_sts.edn_enable_field_alert.de = edn_enable_pfa;
Tests: T1 T2 T3
426 1/1 assign hw2reg.recov_alert_sts.edn_enable_field_alert.d = edn_enable_pfa;
Tests: T1 T2 T3
427
428 for (genvar i = int'(FatalErr); i < LastEdnEntry; i = i+1) begin : gen_mubi_en_copies
429 19/19 assign edn_enable_fo[i] = mubi4_test_true_strict(mubi_edn_enable_fanout[i]);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
430 end : gen_mubi_en_copies
431
432 prim_mubi4_sync #(
433 .NumCopies(EdnEnableCopies),
434 .AsyncOn(0)
435 ) u_prim_mubi4_sync_edn_enable (
436 .clk_i,
437 .rst_ni,
438 .mubi_i(mubi_edn_enable),
439 .mubi_o(mubi_edn_enable_fanout)
440 );
441
442 // SEC_CM: CONFIG.MUBI
443 mubi4_t mubi_cmd_fifo_rst;
444 1/1 assign mubi_cmd_fifo_rst = mubi4_t'(reg2hw.ctrl.cmd_fifo_rst.q);
Tests: T1 T2 T3
445 1/1 assign cmd_fifo_rst_pfa = mubi4_test_invalid(mubi_cmd_fifo_rst_fanout[0]);
Tests: T1 T2 T3
446 1/1 assign hw2reg.recov_alert_sts.cmd_fifo_rst_field_alert.de = cmd_fifo_rst_pfa;
Tests: T1 T2 T3
447 1/1 assign hw2reg.recov_alert_sts.cmd_fifo_rst_field_alert.d = cmd_fifo_rst_pfa;
Tests: T1 T2 T3
448
449 for (genvar i = 1; i < FifoRstCopies; i = i+1) begin : gen_mubi_rst_copies
450 3/3 assign cmd_fifo_rst_fo[i] = mubi4_test_true_strict(mubi_cmd_fifo_rst_fanout[i]);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
451 end : gen_mubi_rst_copies
452
453 prim_mubi4_sync #(
454 .NumCopies(FifoRstCopies),
455 .AsyncOn(0)
456 ) u_prim_mubi4_sync_cmd_fifo_rst (
457 .clk_i,
458 .rst_ni,
459 .mubi_i(mubi_cmd_fifo_rst),
460 .mubi_o(mubi_cmd_fifo_rst_fanout)
461 );
462
463 // counter errors
464 1/1 assign edn_cntr_err = max_reqs_cnt_err;
Tests: T1 T2 T3
465
466 //--------------------------------------------
467 // sw register interface
468 //--------------------------------------------
469 // SEC_CM: CONFIG.MUBI
470 mubi4_t mubi_auto_req_mode;
471 1/1 assign mubi_auto_req_mode = mubi4_t'(reg2hw.ctrl.auto_req_mode.q);
Tests: T1 T2 T3
472 1/1 assign auto_req_mode_pfe = mubi4_test_true_strict(mubi_auto_req_mode_fanout[0]);
Tests: T1 T2 T3
473 1/1 assign auto_req_mode_pfa = mubi4_test_invalid(mubi_auto_req_mode_fanout[1]);
Tests: T1 T2 T3
474 1/1 assign hw2reg.recov_alert_sts.auto_req_mode_field_alert.de = auto_req_mode_pfa;
Tests: T1 T2 T3
475 1/1 assign hw2reg.recov_alert_sts.auto_req_mode_field_alert.d = auto_req_mode_pfa;
Tests: T1 T2 T3
476
477 prim_mubi4_sync #(
478 .NumCopies(2),
479 .AsyncOn(0)
480 ) u_prim_mubi4_sync_auto_req_mode (
481 .clk_i,
482 .rst_ni,
483 .mubi_i(mubi_auto_req_mode),
484 .mubi_o(mubi_auto_req_mode_fanout)
485 );
486
487
488 // SW interface connection
489 // cmd req
490 1/1 assign sw_cmd_req_load = reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q;
Tests: T1 T2 T3
491 1/1 assign sw_cmd_req_bus = reg2hw.sw_cmd_req.q;
Tests: T1 T2 T3
492
493 1/1 assign max_reqs_between_reseed_load = reg2hw.max_num_reqs_between_reseeds.qe;
Tests: T1 T2 T3
494 1/1 assign max_reqs_between_reseed_bus = reg2hw.max_num_reqs_between_reseeds.q;
Tests: T1 T2 T3
495
496 1/1 assign reseed_cmd_load = reg2hw.reseed_cmd.qe;
Tests: T5 T9 T10
497 1/1 assign reseed_cmd_bus = reg2hw.reseed_cmd.q;
Tests: T1 T2 T3
498
499 1/1 assign generate_cmd_load = reg2hw.generate_cmd.qe;
Tests: T5 T9 T10
500 1/1 assign generate_cmd_bus = reg2hw.generate_cmd.q;
Tests: T1 T2 T3
501
502 1/1 assign cs_cmd_handshake = cs_cmd_req_vld_out_q && send_cs_cmd_gated;
Tests: T1 T2 T3
503 1/1 assign gencmd_handshake = cs_cmd_req_vld_out_q && send_gencmd_gated;
Tests: T1 T2 T3
504 1/1 assign rescmd_handshake = cs_cmd_req_vld_out_q && send_rescmd_gated;
Tests: T1 T2 T3
505
506 // The cs_cmd_req register feeds commands from the EDN TL-UL registers to the output register.
507 1/1 assign cs_cmd_req_d =
Tests: T1 T2 T3
508 (!edn_enable_fo[CsrngCmdReq]) ? '0 :
509 boot_wr_ins_cmd ? boot_ins_cmd :
510 boot_wr_gen_cmd ? boot_gen_cmd :
511 boot_wr_uni_cmd ? edn_pkg::BOOT_UNINSTANTIATE :
512 sw_cmd_req_load ? sw_cmd_req_bus :
513 cs_cmd_req_q;
514
515 // The cs_cmd_req_vld register handles the valid signal that is sent along with cs_cmd_req_q.
516 1/1 assign cs_cmd_req_vld_d =
Tests: T1 T2 T3
517 (!edn_enable_fo[CsrngCmdReqValid]) ? '0 :
518 cs_cmd_handshake ? '0 :
519 (sw_cmd_req_load || boot_wr_ins_cmd ||
520 boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 :
521 cs_cmd_req_vld_q; // cmd reg write
522
523 1/1 assign send_cs_cmd_gated = cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready;
Tests: T1 T2 T3
524
525 // The cs_cmd_req_out register feeds the commands coming from the auto mode FIFOs
526 // or the cs_cmd_req register to the CSRNG.
527 1/1 assign cs_cmd_req_out_d =
Tests: T1 T2 T3
528 (!edn_enable_fo[CsrngCmdReqOut]) ? '0 :
529 // Update the output value with the next word of the reseed command in auto mode.
530 (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ?
531 sfifo_rescmd_rdata :
532 cs_cmd_req_out_q) :
533 // Update the output value with the next word of the generate command in auto mode.
534 (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ?
535 sfifo_gencmd_rdata :
536 cs_cmd_req_out_q) :
537 // Update the output value with the next word of the cs_cmd_req register.
538 (cs_cmd_req_vld_q && !cs_cmd_handshake) ? cs_cmd_req_q :
539 cs_cmd_req_out_q;
540
541 // Hold the valid until completing the valid/ready handshake. This is required to not violate
542 // the valid/ready protocol in case of acknowledgement errors received from CSRNG.
543 1/1 assign cs_cmd_req_vld_hold_d =
Tests: T1 T2 T3
544 (!edn_enable_fo[CsrngCmdReqValidOut]) ? 1'b0 :
545 (cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q) && !csrng_cmd_i.csrng_req_ready;
546
547 // The cs_cmd_req_vld_out register handles the valid signal that is sent along with
548 // cs_cmd_req_out. Unless EDN is disabled, the valid must not be dropped before seeing the
549 // ready.
550 1/1 assign cs_cmd_req_vld_out_d =
Tests: T1 T2 T3
551 (!edn_enable_fo[CsrngCmdReqValidOut]) ? '0 :
552 cmd_sent ? '0 :
553 (send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 :
554 (send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 :
555 cs_cmd_req_vld_q && !cs_cmd_handshake;
556
557 // drive outputs
558 1/1 assign csrng_cmd_o.csrng_req_valid =
Tests: T1 T2 T3
559 (cs_cmd_req_vld_out_q && !reject_csrng_entropy) || cs_cmd_req_vld_hold_q;
560 1/1 assign csrng_cmd_o.csrng_req_bus = cs_cmd_req_out_q;
Tests: T1 T2 T3
561
562 // Accept a new command only if no command is currently being written to SW_CMD_REQ
563 // and the register is ready for the next word.
564 assign hw2reg.sw_cmd_sts.cmd_rdy.de = 1'b1;
565 1/1 assign hw2reg.sw_cmd_sts.cmd_rdy.d = cmd_rdy;
Tests: T1 T2 T3
566 1/1 assign cmd_rdy = !sw_cmd_req_load && cmd_rdy_d && cmd_reg_rdy_d;
Tests: T1 T2 T3
567 // We accept SW commands only in SW or auto mode.
568 // In auto mode, sw_cmd_mode will transition to low after the initial instantiate command.
569 // In SW mode, cmd_rdy is low when a previous command has not been acked yet.
570 1/1 assign cmd_rdy_d =
Tests: T1 T2 T3
571 !edn_enable_fo[SwCmdSts] ? 1'b0 :
572 !sw_cmd_mode ? 1'b0 :
573 reject_csrng_entropy ? 1'b0 :
574 sw_cmd_req_load ? 1'b0 :
575 accept_sw_cmds_pulse ? 1'b1 :
576 csrng_cmd_i.csrng_rsp_ack ? 1'b1 :
577 cmd_rdy_q;
578
579 // cmd_reg_rdy_d is high if SW_CMD_REQ is ready to accept a new word.
580 assign hw2reg.sw_cmd_sts.cmd_reg_rdy.de = 1'b1;
581 1/1 assign hw2reg.sw_cmd_sts.cmd_reg_rdy.d = cmd_reg_rdy_d;
Tests: T1 T2 T3
582 1/1 assign cmd_reg_rdy_d =
Tests: T1 T2 T3
583 !edn_enable_fo[SwCmdSts] ? 1'b0 :
584 !sw_cmd_mode ? 1'b0 :
585 reject_csrng_entropy ? 1'b0 :
586 sw_cmd_req_load ? 1'b0 :
587 accept_sw_cmds_pulse ? 1'b1 :
588 cs_cmd_handshake ? 1'b1 :
589 cmd_reg_rdy_q;
590
591 // Whenever a sw_cmd_req is acked by CSRNG, update the command status.
592 assign hw2reg.sw_cmd_sts.cmd_sts.de = 1'b1;
593 1/1 assign hw2reg.sw_cmd_sts.cmd_sts.d = csrng_cmd_sts_d;
Tests: T1 T2 T3
594 1/1 assign csrng_cmd_sts_d =
Tests: T1 T2 T3
595 !edn_enable_fo[SwCmdSts] ? csrng_pkg::CMD_STS_SUCCESS :
596 csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode &&
597 !reject_csrng_entropy ? csrng_cmd_i.csrng_rsp_sts :
598 csrng_cmd_sts_q;
599
600 // cmd_ack goes high only when a command is acknowledged that has been loaded into sw_cmd_req.
601 assign hw2reg.sw_cmd_sts.cmd_ack.de = 1'b1;
602 1/1 assign hw2reg.sw_cmd_sts.cmd_ack.d = csrng_sw_cmd_ack_d;
Tests: T1 T2 T3
603 1/1 assign csrng_sw_cmd_ack_d =
Tests: T1 T2 T3
604 !edn_enable_fo[SwCmdSts] ? 1'b0 :
605 sw_cmd_req_load ? 1'b0 :
606 csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && !reject_csrng_entropy ? 1'b1 :
607 csrng_sw_cmd_ack_q;
608
609 //--------------------------------------------
610 // hw_cmd_sts register
611 //--------------------------------------------
612 1/1 assign main_sm_idle = (edn_main_sm_state == Idle);
Tests: T1 T2 T3
613 1/1 assign cs_hw_cmd_handshake = !sw_cmd_mode && csrng_cmd_o.csrng_req_valid &&
Tests: T1 T2 T3
614 csrng_cmd_i.csrng_req_ready;
615 1/1 assign cs_hw_cmd_handshake_1st = cs_hw_cmd_handshake &&
Tests: T1 T2 T3
616 ((send_rescmd || capt_rescmd_fifo_cnt ||
617 send_gencmd || capt_gencmd_fifo_cnt) ? cmd_hdr_busy_q : 1'b1);
618
619 // Set the boot_mode field to one when boot mode is entered and to zero when it is left.
620 assign hw2reg.hw_cmd_sts.boot_mode.de = 1'b1;
621 1/1 assign hw2reg.hw_cmd_sts.boot_mode.d = boot_mode_d;
Tests: T1 T2 T3
622 1/1 assign boot_mode_d = main_sm_done_pulse || main_sm_idle ? 1'b0 :
Tests: T1 T2 T3
623 boot_send_ins_cmd && cs_hw_cmd_handshake ? 1'b1 :
624 boot_mode_q;
625 // Set the auto_mode field to one when auto mode is entered and to zero when it is left. In case
626 // the first handshake in automode leads to an error, we still set the auto_mode field to know
627 // that the error happened upon entering auto mode.
628 assign hw2reg.hw_cmd_sts.auto_mode.de = 1'b1;
629 1/1 assign hw2reg.hw_cmd_sts.auto_mode.d = auto_mode_d;
Tests: T1 T2 T3
630 1/1 assign auto_mode_d = main_sm_done_pulse || main_sm_idle ? 1'b0 :
Tests: T1 T2 T3
631 auto_req_mode_busy && cs_hw_cmd_handshake ? 1'b1 :
632 auto_mode_q;
633 // Record the cmd_sts signal each time a hardware command is acknowledged.
634 // Reset it each time a new hardware command is issued. In case we saw an error previously,
635 // keep status returned with the error.
636 assign hw2reg.hw_cmd_sts.cmd_sts.de = 1'b1;
637 1/1 assign hw2reg.hw_cmd_sts.cmd_sts.d = csrng_hw_cmd_sts_d;
Tests: T1 T2 T3
638 1/1 assign csrng_hw_cmd_sts_d =
Tests: T1 T2 T3
639 !edn_enable_fo[HwCmdSts] ? csrng_pkg::CMD_STS_SUCCESS :
640 csrng_cmd_i.csrng_rsp_ack && !sw_cmd_mode &&
641 !reject_csrng_entropy ? csrng_cmd_i.csrng_rsp_sts :
642 reject_csrng_entropy ? csrng_hw_cmd_sts_q :
643 cs_hw_cmd_handshake ? csrng_pkg::CMD_STS_SUCCESS :
644 csrng_hw_cmd_sts_q;
645 // Set the cmd_ack signal to high whenever a hardware command is acknowledged and set it
646 // to low whenever a new hardware command is issued to the CSRNG. Don't clear it in case we saw
647 // an error previously.
648 assign hw2reg.hw_cmd_sts.cmd_ack.de = 1'b1;
649 1/1 assign hw2reg.hw_cmd_sts.cmd_ack.d = csrng_hw_cmd_ack_d;
Tests: T1 T2 T3
650 1/1 assign csrng_hw_cmd_ack_d =
Tests: T1 T2 T3
651 !edn_enable_fo[HwCmdSts] ? 1'b0 :
652 csrng_cmd_i.csrng_rsp_ack && !sw_cmd_mode && !reject_csrng_entropy ? 1'b1 :
653 reject_csrng_entropy ? csrng_hw_cmd_ack_q :
654 cs_hw_cmd_handshake ? 1'b0 :
655 csrng_hw_cmd_ack_q;
656 // Set the cmd_type to the application command type value of the hardware controlled
657 // command issued last. Only the command header but not the additional data matters.
658 // Don't update it in case we saw an error previously.
659 assign hw2reg.hw_cmd_sts.cmd_type.de = 1'b1;
660 1/1 assign hw2reg.hw_cmd_sts.cmd_type.d = cmd_type_d;
Tests: T1 T2 T3
661 1/1 assign cmd_type_d =
Tests: T1 T2 T3
662 !edn_enable_fo[HwCmdSts] ? {1'b0, csrng_pkg::INV} :
663 reject_csrng_entropy ? cmd_type_q :
664 cs_hw_cmd_handshake_1st ? cs_cmd_req_out_q[3:0] : cmd_type_q;
665
666 // rescmd fifo
667 // SEC_CM: FIFO.CTR.REDUN
668 prim_fifo_sync #(
669 .Width(RescmdFifoWidth),
670 .Pass(0),
671 .Depth(RescmdFifoDepth),
672 .OutputZeroIfEmpty(0),
673 .Secure(1)
674 ) u_prim_fifo_sync_rescmd (
675 .clk_i (clk_i),
676 .rst_ni (rst_ni),
677 .clr_i (sfifo_rescmd_clr),
678 .wvalid_i (sfifo_rescmd_push),
679 .wready_o (),
680 .wdata_i (sfifo_rescmd_wdata),
681 .rvalid_o (sfifo_rescmd_not_empty),
682 .rready_i (sfifo_rescmd_pop),
683 .rdata_o (sfifo_rescmd_rdata),
684 .full_o (sfifo_rescmd_full),
685 .depth_o (sfifo_rescmd_depth),
686 .err_o (sfifo_rescmd_int_err)
687 );
688
689 // Gate rescmd FIFO operations in case of CSRNG backpressure.
690 1/1 assign send_rescmd_gated = (send_rescmd || capt_rescmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready;
Tests: T1 T2 T3
691
692 1/1 assign sfifo_rescmd_push =
Tests: T5 T9 T10
693 rescmd_handshake ? 1'b1 :
694 reseed_cmd_load;
695
696 1/1 assign sfifo_rescmd_wdata =
Tests: T1 T2 T3
697 auto_req_mode_busy ? cs_cmd_req_out_q :
698 reseed_cmd_bus;
699
700 1/1 assign sfifo_rescmd_pop = (rescmd_handshake && !cmd_sent) || capt_rescmd_fifo_cnt;
Tests: T1 T2 T3
701
702 1/1 assign sfifo_rescmd_clr = (cmd_fifo_rst_fo[1] || main_sm_done_pulse);
Tests: T1 T2 T3
703
704 1/1 assign sfifo_rescmd_err =
Tests: T1 T2 T3
705 {(sfifo_rescmd_push && sfifo_rescmd_full),
706 (sfifo_rescmd_pop && !sfifo_rescmd_not_empty),
707 (sfifo_rescmd_full && !sfifo_rescmd_not_empty) || sfifo_rescmd_int_err};
708
709 // gencmd fifo
710 // SEC_CM: FIFO.CTR.REDUN
711 prim_fifo_sync #(
712 .Width(GencmdFifoWidth),
713 .Pass(0),
714 .Depth(GencmdFifoDepth),
715 .OutputZeroIfEmpty(0),
716 .Secure(1)
717 ) u_prim_fifo_sync_gencmd (
718 .clk_i (clk_i),
719 .rst_ni (rst_ni),
720 .clr_i (sfifo_gencmd_clr),
721 .wvalid_i (sfifo_gencmd_push),
722 .wready_o (),
723 .wdata_i (sfifo_gencmd_wdata),
724 .rvalid_o (sfifo_gencmd_not_empty),
725 .rready_i (sfifo_gencmd_pop),
726 .rdata_o (sfifo_gencmd_rdata),
727 .full_o (sfifo_gencmd_full),
728 .depth_o (sfifo_gencmd_depth),
729 .err_o (sfifo_gencmd_int_err)
730 );
731
732 // Gate gencmd FIFO operations in case of CSRNG backpressure.
733 1/1 assign send_gencmd_gated = (send_gencmd || capt_gencmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready;
Tests: T1 T2 T3
734
735 1/1 assign sfifo_gencmd_push =
Tests: T5 T9 T10
736 gencmd_handshake ? 1'b1 :
737 generate_cmd_load;
738
739 1/1 assign sfifo_gencmd_wdata =
Tests: T1 T2 T3
740 auto_req_mode_busy ? cs_cmd_req_out_q :
741 generate_cmd_bus;
742
743 1/1 assign sfifo_gencmd_pop = (gencmd_handshake && !cmd_sent) || capt_gencmd_fifo_cnt;
Tests: T1 T2 T3
744
745 1/1 assign sfifo_gencmd_clr = (cmd_fifo_rst_fo[2] || main_sm_done_pulse);
Tests: T1 T2 T3
746
747 1/1 assign sfifo_gencmd_err =
Tests: T1 T2 T3
748 {(sfifo_gencmd_push && sfifo_gencmd_full),
749 (sfifo_gencmd_pop && !sfifo_gencmd_not_empty),
750 (sfifo_gencmd_full && !sfifo_gencmd_not_empty) || sfifo_gencmd_int_err};
751
752 // sm to process csrng commands
753 // SEC_CM: MAIN_SM.FSM.SPARSE
754 // SEC_CM: MAIN_SM.CTR.LOCAL_ESC
755 edn_main_sm u_edn_main_sm (
756 .clk_i (clk_i),
757 .rst_ni (rst_ni),
758 .edn_enable_i (edn_enable_fo[MainFsmEn]),
759 .boot_req_mode_i (boot_req_mode_fo[1]),
760 .auto_req_mode_i (auto_req_mode_pfe),
761 .sw_cmd_req_load_i (sw_cmd_req_load),
762 .sw_cmd_mode_o (sw_cmd_mode),
763 .boot_wr_ins_cmd_o (boot_wr_ins_cmd),
764 .boot_send_ins_cmd_o (boot_send_ins_cmd),
765 .boot_wr_gen_cmd_o (boot_wr_gen_cmd),
766 .boot_wr_uni_cmd_o (boot_wr_uni_cmd),
767 .accept_sw_cmds_pulse_o (accept_sw_cmds_pulse),
768 .main_sm_done_pulse_o (main_sm_done_pulse),
769 .csrng_cmd_ack_i (csrng_cmd_i.csrng_rsp_ack),
770 .capt_gencmd_fifo_cnt_o (capt_gencmd_fifo_cnt),
771 .send_gencmd_o (send_gencmd),
772 .max_reqs_cnt_zero_i (max_reqs_cnt_zero),
773 .capt_rescmd_fifo_cnt_o (capt_rescmd_fifo_cnt),
774 .send_rescmd_o (send_rescmd),
775 .cmd_sent_i (cmd_sent),
776 .auto_req_mode_busy_o (auto_req_mode_busy),
777 .main_sm_state_o (edn_main_sm_state),
778 .csrng_ack_err_i (csrng_ack_err),
779 .reject_csrng_entropy_o (reject_csrng_entropy),
780 .local_escalate_i (fatal_loc_events),
781 .main_sm_err_o (edn_main_sm_err)
782 );
783
784
785 // Maximum requests counter for a generate command
786
787 // SEC_CM: CTR.REDUN
788 prim_count #(
789 .Width(RegWidth),
790 .ResetValue(edn_reg_pkg::MaxNumReqsBetweenReseedsResval)
791 ) u_prim_count_max_reqs_cntr (
792 .clk_i,
793 .rst_ni,
794 .clr_i(1'b0),
795 .set_i(max_reqs_cnt_load),
796 .set_cnt_i(max_reqs_between_reseed_bus),
797 .incr_en_i(1'b0),
798 .decr_en_i(send_gencmd && cmd_sent), // count down
799 .step_i(RegWidth'(1)),
800 .commit_i(1'b1),
801 .cnt_o(max_reqs_cnt),
802 .cnt_after_commit_o(),
803 .err_o(max_reqs_cnt_err)
804 );
805
806
807 1/1 assign max_reqs_cnt_load = (max_reqs_between_reseed_load || // sw initial load
Tests: T1 T2 T3
808 send_rescmd && cmd_sent || // runtime decrement
809 main_sm_done_pulse); // restore when auto mode done
810
811 1/1 assign max_reqs_cnt_zero = (max_reqs_cnt == '0);
Tests: T1 T2 T3
812
813
814 1/1 assign cmd_fifo_cnt_d =
Tests: T1 T2 T3
815 (!edn_enable_fo[CmdFifoCnt]) ? '0 :
816 (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 :
817 capt_gencmd_fifo_cnt ? sfifo_gencmd_depth :
818 capt_rescmd_fifo_cnt ? sfifo_rescmd_depth :
819 (sfifo_gencmd_pop || sfifo_rescmd_pop) ? (cmd_fifo_cnt_q-1) :
820 cmd_fifo_cnt_q;
821
822 // Consider a reseed command as sent if all values have been popped from the queue once
823 // and the handshake with CSRNG happend for the last word.
824 1/1 assign cmd_sent = (cmd_fifo_cnt_q == RescmdFifoIdxWidth'(1)) &&
Tests: T1 T2 T3
825 (gencmd_handshake || rescmd_handshake);
826
827 // Track whether we're currently sending the command header of a hardware Reseed or Generate
828 // command.
829 1/1 assign cmd_hdr_busy_d =
Tests: T1 T2 T3
830 capt_gencmd_fifo_cnt || capt_rescmd_fifo_cnt ? 1'b1 :
831 cs_hw_cmd_handshake ? 1'b0 : cmd_hdr_busy_q;
832
833 // SEC_CM: CONFIG.MUBI
834 mubi4_t mubi_boot_req_mode;
835 1/1 assign mubi_boot_req_mode = mubi4_t'(reg2hw.ctrl.boot_req_mode.q);
Tests: T1 T2 T3
836 1/1 assign boot_req_mode_pfa = mubi4_test_invalid(mubi_boot_req_mode_fanout[0]);
Tests: T1 T2 T3
837 1/1 assign hw2reg.recov_alert_sts.boot_req_mode_field_alert.de = boot_req_mode_pfa;
Tests: T1 T2 T3
838 1/1 assign hw2reg.recov_alert_sts.boot_req_mode_field_alert.d = boot_req_mode_pfa;
Tests: T1 T2 T3
839
840 for (genvar i = 1; i < BootReqCopies; i = i+1) begin : gen_mubi_boot_copies
841 1/1 assign boot_req_mode_fo[i] = mubi4_test_true_strict(mubi_boot_req_mode_fanout[i]);
Tests: T1 T2 T3
842 end : gen_mubi_boot_copies
843
844 prim_mubi4_sync #(
845 .NumCopies(BootReqCopies),
846 .AsyncOn(0)
847 ) u_prim_mubi4_sync_boot_req_mode (
848 .clk_i,
849 .rst_ni,
850 .mubi_i(mubi_boot_req_mode),
851 .mubi_o(mubi_boot_req_mode_fanout)
852 );
853
854
855 //--------------------------------------------
856 // packer arbitration
857 //--------------------------------------------
858
859 prim_arbiter_ppc #(
860 .EnDataPort(0), // Ignore data port
861 .N(NumEndPoints), // Number of request ports
862 .DW(1) // Data width
863 ) u_prim_arbiter_ppc_packer_arb (
864 .clk_i(clk_i),
865 .rst_ni(rst_ni),
866 .req_chk_i(1'b1),
867 .req_i(packer_arb_req), // N number of reqs
868 .data_i('{default: 1'b0}),
869 .gnt_o(packer_arb_gnt), // N number of gnts
870 .idx_o(), //NC
871 .valid_o(packer_arb_valid),
872 .data_o(), // NC
873 .ready_i(packer_arb_ready)
874 );
875
876 for (genvar i = 0; i < NumEndPoints; i=i+1) begin : gen_arb
877 7/7 assign packer_arb_req[i] = !packer_ep_rvalid[i] && edn_i[i].edn_req;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
878 end
879
880 //--------------------------------------------
881 // csrng interface packer
882 //--------------------------------------------
883
884 prim_packer_fifo #(
885 .InW(CSGenBitsWidth),
886 .OutW(CSGenBitsWidth),
887 .ClearOnRead(1'b0)
888 ) u_prim_packer_fifo_cs (
889 .clk_i (clk_i),
890 .rst_ni (rst_ni),
891 .clr_i (packer_cs_clr),
892 .wvalid_i (packer_cs_push),
893 .wdata_i (packer_cs_wdata),
894 .wready_o (packer_cs_wready),
895 .rvalid_o (packer_cs_rvalid),
896 .rdata_o (packer_cs_rdata),
897 .rready_i (packer_cs_rready),
898 .depth_o ()
899 );
900
901 1/1 assign packer_cs_clr = !edn_enable_fo[CsrngPackerClr];
Tests: T1 T2 T3
902 1/1 assign packer_cs_push = csrng_cmd_i.genbits_valid && !reject_csrng_entropy &&
Tests: T1 T2 T3
903 !((csrng_cmd_i.csrng_rsp_sts != csrng_pkg::CMD_STS_SUCCESS) &&
904 csrng_cmd_i.csrng_rsp_ack);
905 1/1 assign packer_cs_wdata = csrng_cmd_i.genbits_bus;
Tests: T1 T2 T3
906 1/1 assign csrng_cmd_o.genbits_ready = packer_cs_wready && !reject_csrng_entropy;
Tests: T1 T2 T3
907 1/1 assign packer_cs_rready = packer_arb_valid;
Tests: T1 T2 T3
908 1/1 assign packer_arb_ready = packer_cs_rvalid;
Tests: T1 T2 T3
909
910 1/1 assign csrng_fips_d =
Tests: T1 T2 T3
911 !edn_enable_fo[CsrngFipsEn] ? 1'b0 :
912 (packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips :
913 csrng_fips_q;
914
915 //--------------------------------------------
916 // data path integrity check
917 // - a counter measure to software genbits bus tampering
918 // - checks to make sure repeated data sets off
919 // an alert for sw to handle
920 //--------------------------------------------
921
922 // SEC_CM: CS_RDATA.BUS.CONSISTENCY
923
924 // capture a copy of the entropy data
925 1/1 assign cs_rdata_capt_vld = (packer_cs_rvalid && packer_cs_rready);
Tests: T1 T2 T3
926
927 1/1 assign cs_rdata_capt_d = cs_rdata_capt_vld ? packer_cs_rdata[63:0] : cs_rdata_capt_q;
Tests: T1 T2 T3
928
929 1/1 assign cs_rdata_capt_vld_d =
Tests: T1 T2 T3
930 !edn_enable_fo[CsrngDataVld] ? 1'b0 :
931 cs_rdata_capt_vld ? 1'b1 :
932 cs_rdata_capt_vld_q;
933
934 // continuous compare of the entropy data
935 1/1 assign edn_bus_cmp_alert = cs_rdata_capt_vld && cs_rdata_capt_vld_q &&
Tests: T1 T2 T3
936 (cs_rdata_capt_q == packer_cs_rdata[63:0]);
937
938 1/1 assign hw2reg.recov_alert_sts.edn_bus_cmp_alert.de = edn_bus_cmp_alert;
Tests: T3 T23 T6
939 1/1 assign hw2reg.recov_alert_sts.edn_bus_cmp_alert.d = edn_bus_cmp_alert;
Tests: T3 T23 T6
940
941 //--------------------------------------------
942 // end point interface packers generation
943 //--------------------------------------------
944
945 for (genvar i = 0; i < NumEndPoints; i=i+1) begin : gen_ep_blk
946 prim_packer_fifo #(
947 .InW(CSGenBitsWidth),
948 .OutW(EndPointBusWidth),
949 .ClearOnRead(1'b0)
950 ) u_prim_packer_fifo_ep (
951 .clk_i (clk_i),
952 .rst_ni (rst_ni),
953 .clr_i (packer_ep_clr[i]),
954 .wvalid_i (packer_ep_push[i]),
955 .wdata_i (packer_ep_wdata[i]),
956 .wready_o (packer_ep_wready[i]),
957 .rvalid_o (packer_ep_rvalid[i]),
958 .rdata_o (packer_ep_rdata[i]),
959 .rready_i (packer_ep_rready[i]),
960 .depth_o ()
961 );
962
963 7/7 assign packer_ep_push[i] = packer_arb_valid && packer_ep_wready[i] && packer_arb_gnt[i];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
964 7/7 assign packer_ep_wdata[i] = packer_cs_rdata;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
965
966 // fips indication
967 7/7 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
969 edn_fips_q[i];
970 7/7 assign edn_o[i].edn_fips = edn_fips_q[i];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
971
972 // gate returned data
973 7/7 assign edn_o[i].edn_ack = packer_ep_ack[i];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
974 7/7 assign edn_o[i].edn_bus = packer_ep_rdata[i];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
975
976 // SEC_CM: ACK_SM.FSM.SPARSE
977 edn_ack_sm u_edn_ack_sm_ep (
978 .clk_i (clk_i),
979 .rst_ni (rst_ni),
980 .enable_i (edn_enable_fo[AckFsmEn]),
981 .req_i (edn_i[i].edn_req),
982 .ack_o (packer_ep_ack[i]),
983 .fifo_not_empty_i (packer_ep_rvalid[i]),
984 .fifo_pop_o (packer_ep_rready[i]),
985 .fifo_clr_o (packer_ep_clr[i]),
986 .local_escalate_i (fatal_loc_events),
987 .ack_sm_err_o (edn_ack_sm_err[i])
988 );
989
990 end
991
992 // state machine status
993 assign hw2reg.main_sm_state.de = 1'b1;
994 1/1 assign hw2reg.main_sm_state.d = edn_main_sm_state;
Tests: T1 T2 T3
995
996 //--------------------------------------------
997 // Assertions
998 //--------------------------------------------
999 // Do not accept new genbits into the CSRNG interface genbits FIFO if we are in the alert state
1000 // due to a CSRNG status error response.
1001 `ASSERT(CsErrAcceptNoEntropy_A, reject_csrng_entropy |-> packer_cs_push == 0)
1002 // Do not issue new commands to the CSRNG if we are in the alert state due to a CSRNG status
1003 // error response. The only exception is if we need to hold the valid to complete a started
1004 // handshake.
1005 `ASSERT(CsErrIssueNoCommands_A, reject_csrng_entropy |->
1006 csrng_cmd_o.csrng_req_valid == 0 || cs_cmd_req_vld_hold_q == 1'b1)
1007
1008 //--------------------------------------------
1009 // unused signals
1010 //--------------------------------------------
1011
1012 1/1 assign unused_err_code_test_bit = (|err_code_test_bit[19:2]) || (|err_code_test_bit[27:22]);
Tests: T1 T2 T3
Cond Coverage for Module :
edn_core
| Total | Covered | Percent |
|---|
| Conditions | 680 | 619 | 91.03 |
| Logical | 680 | 619 | 91.03 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Module :
edn_core
| Line No. | Total | Covered | Percent |
| Branches |
|
113 |
111 |
98.23 |
| TERNARY |
507 |
6 |
6 |
100.00 |
| TERNARY |
516 |
4 |
4 |
100.00 |
| TERNARY |
527 |
7 |
7 |
100.00 |
| TERNARY |
543 |
2 |
2 |
100.00 |
| TERNARY |
550 |
5 |
5 |
100.00 |
| TERNARY |
570 |
7 |
6 |
85.71 |
| TERNARY |
582 |
7 |
6 |
85.71 |
| TERNARY |
594 |
3 |
3 |
100.00 |
| TERNARY |
603 |
4 |
4 |
100.00 |
| TERNARY |
622 |
3 |
3 |
100.00 |
| TERNARY |
630 |
3 |
3 |
100.00 |
| TERNARY |
638 |
5 |
5 |
100.00 |
| TERNARY |
650 |
5 |
5 |
100.00 |
| TERNARY |
661 |
4 |
4 |
100.00 |
| TERNARY |
692 |
2 |
2 |
100.00 |
| TERNARY |
696 |
2 |
2 |
100.00 |
| TERNARY |
735 |
2 |
2 |
100.00 |
| TERNARY |
739 |
2 |
2 |
100.00 |
| TERNARY |
814 |
6 |
6 |
100.00 |
| TERNARY |
829 |
3 |
3 |
100.00 |
| TERNARY |
910 |
3 |
3 |
100.00 |
| TERNARY |
927 |
2 |
2 |
100.00 |
| TERNARY |
929 |
3 |
3 |
100.00 |
| TERNARY |
967 |
3 |
3 |
100.00 |
| TERNARY |
967 |
3 |
3 |
100.00 |
| TERNARY |
967 |
3 |
3 |
100.00 |
| TERNARY |
967 |
3 |
3 |
100.00 |
| TERNARY |
967 |
3 |
3 |
100.00 |
| TERNARY |
967 |
3 |
3 |
100.00 |
| TERNARY |
967 |
3 |
3 |
100.00 |
| IF |
223 |
2 |
2 |
100.00 |
507 assign cs_cmd_req_d =
508 (!edn_enable_fo[CsrngCmdReq]) ? '0 :
-1-
==>
509 boot_wr_ins_cmd ? boot_ins_cmd :
-2-
==>
510 boot_wr_gen_cmd ? boot_gen_cmd :
-3-
==>
511 boot_wr_uni_cmd ? edn_pkg::BOOT_UNINSTANTIATE :
-4-
==>
512 sw_cmd_req_load ? sw_cmd_req_bus :
-5-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
Covered |
T3,T22,T23 |
| 0 |
0 |
1 |
- |
- |
Covered |
T3,T22,T23 |
| 0 |
0 |
0 |
1 |
- |
Covered |
T3,T23,T28 |
| 0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
516 assign cs_cmd_req_vld_d =
517 (!edn_enable_fo[CsrngCmdReqValid]) ? '0 :
-1-
==>
518 cs_cmd_handshake ? '0 :
-2-
==>
519 (sw_cmd_req_load || boot_wr_ins_cmd ||
520 boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 :
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
527 assign cs_cmd_req_out_d =
528 (!edn_enable_fo[CsrngCmdReqOut]) ? '0 :
-1-
==>
529 // Update the output value with the next word of the reseed command in auto mode.
530 (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ?
-2- -3-
==>
==>
531 sfifo_rescmd_rdata :
532 cs_cmd_req_out_q) :
533 // Update the output value with the next word of the generate command in auto mode.
534 (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ?
-4- -5-
==>
==>
535 sfifo_gencmd_rdata :
536 cs_cmd_req_out_q) :
537 // Update the output value with the next word of the cs_cmd_req register.
538 (cs_cmd_req_vld_q && !cs_cmd_handshake) ? cs_cmd_req_q :
-6-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
- |
- |
Covered |
T5,T9,T7 |
| 0 |
1 |
0 |
- |
- |
- |
Covered |
T5,T9,T7 |
| 0 |
0 |
- |
1 |
1 |
- |
Covered |
T5,T9,T7 |
| 0 |
0 |
- |
1 |
0 |
- |
Covered |
T5,T9,T7 |
| 0 |
0 |
- |
0 |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
0 |
- |
0 |
Covered |
T1,T2,T3 |
543 assign cs_cmd_req_vld_hold_d =
544 (!edn_enable_fo[CsrngCmdReqValidOut]) ? 1'b0 :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
550 assign cs_cmd_req_vld_out_d =
551 (!edn_enable_fo[CsrngCmdReqValidOut]) ? '0 :
-1-
==>
552 cmd_sent ? '0 :
-2-
==>
553 (send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 :
-3-
==>
554 (send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 :
-4-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T5,T9,T7 |
| 0 |
0 |
1 |
- |
Covered |
T5,T9,T7 |
| 0 |
0 |
0 |
1 |
Covered |
T5,T9,T7 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
570 assign cmd_rdy_d =
571 !edn_enable_fo[SwCmdSts] ? 1'b0 :
-1-
==>
572 !sw_cmd_mode ? 1'b0 :
-2-
==>
573 reject_csrng_entropy ? 1'b0 :
-3-
==>
574 sw_cmd_req_load ? 1'b0 :
-4-
==>
575 accept_sw_cmds_pulse ? 1'b1 :
-5-
==>
576 csrng_cmd_i.csrng_rsp_ack ? 1'b1 :
-6-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T3,T4,T22 |
| 0 |
0 |
1 |
- |
- |
- |
Not Covered |
|
| 0 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
582 assign cmd_reg_rdy_d =
583 !edn_enable_fo[SwCmdSts] ? 1'b0 :
-1-
==>
584 !sw_cmd_mode ? 1'b0 :
-2-
==>
585 reject_csrng_entropy ? 1'b0 :
-3-
==>
586 sw_cmd_req_load ? 1'b0 :
-4-
==>
587 accept_sw_cmds_pulse ? 1'b1 :
-5-
==>
588 cs_cmd_handshake ? 1'b1 :
-6-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T3,T4,T22 |
| 0 |
0 |
1 |
- |
- |
- |
Not Covered |
|
| 0 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
594 assign csrng_cmd_sts_d =
595 !edn_enable_fo[SwCmdSts] ? csrng_pkg::CMD_STS_SUCCESS :
-1-
==>
596 csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode &&
597 !reject_csrng_entropy ? csrng_cmd_i.csrng_rsp_sts :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
603 assign csrng_sw_cmd_ack_d =
604 !edn_enable_fo[SwCmdSts] ? 1'b0 :
-1-
==>
605 sw_cmd_req_load ? 1'b0 :
-2-
==>
606 csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && !reject_csrng_entropy ? 1'b1 :
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
622 assign boot_mode_d = main_sm_done_pulse || main_sm_idle ? 1'b0 :
-1-
==>
623 boot_send_ins_cmd && cs_hw_cmd_handshake ? 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T22,T23 |
| 0 |
0 |
Covered |
T1,T2,T3 |
630 assign auto_mode_d = main_sm_done_pulse || main_sm_idle ? 1'b0 :
-1-
==>
631 auto_req_mode_busy && cs_hw_cmd_handshake ? 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T9,T7 |
| 0 |
0 |
Covered |
T1,T2,T3 |
638 assign csrng_hw_cmd_sts_d =
639 !edn_enable_fo[HwCmdSts] ? csrng_pkg::CMD_STS_SUCCESS :
-1-
==>
640 csrng_cmd_i.csrng_rsp_ack && !sw_cmd_mode &&
641 !reject_csrng_entropy ? csrng_cmd_i.csrng_rsp_sts :
-2-
==>
642 reject_csrng_entropy ? csrng_hw_cmd_sts_q :
-3-
==>
643 cs_hw_cmd_handshake ? csrng_pkg::CMD_STS_SUCCESS :
-4-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T3,T22,T5 |
| 0 |
0 |
1 |
- |
Covered |
T23,T10,T28 |
| 0 |
0 |
0 |
1 |
Covered |
T3,T22,T5 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
650 assign csrng_hw_cmd_ack_d =
651 !edn_enable_fo[HwCmdSts] ? 1'b0 :
-1-
==>
652 csrng_cmd_i.csrng_rsp_ack && !sw_cmd_mode && !reject_csrng_entropy ? 1'b1 :
-2-
==>
653 reject_csrng_entropy ? csrng_hw_cmd_ack_q :
-3-
==>
654 cs_hw_cmd_handshake ? 1'b0 :
-4-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T3,T22,T5 |
| 0 |
0 |
1 |
- |
Covered |
T23,T10,T28 |
| 0 |
0 |
0 |
1 |
Covered |
T3,T22,T5 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
661 assign cmd_type_d =
662 !edn_enable_fo[HwCmdSts] ? {1'b0, csrng_pkg::INV} :
-1-
==>
663 reject_csrng_entropy ? cmd_type_q :
-2-
==>
664 cs_hw_cmd_handshake_1st ? cs_cmd_req_out_q[3:0] : cmd_type_q;
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T23,T10,T28 |
| 0 |
0 |
1 |
Covered |
T3,T22,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
692 assign sfifo_rescmd_push =
693 rescmd_handshake ? 1'b1 :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T9,T7 |
| 0 |
Covered |
T1,T2,T3 |
696 assign sfifo_rescmd_wdata =
697 auto_req_mode_busy ? cs_cmd_req_out_q :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T9,T7 |
| 0 |
Covered |
T1,T2,T3 |
735 assign sfifo_gencmd_push =
736 gencmd_handshake ? 1'b1 :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T9,T7 |
| 0 |
Covered |
T1,T2,T3 |
739 assign sfifo_gencmd_wdata =
740 auto_req_mode_busy ? cs_cmd_req_out_q :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T9,T7 |
| 0 |
Covered |
T1,T2,T3 |
814 assign cmd_fifo_cnt_d =
815 (!edn_enable_fo[CmdFifoCnt]) ? '0 :
-1-
==>
816 (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 :
-2-
==>
817 capt_gencmd_fifo_cnt ? sfifo_gencmd_depth :
-3-
==>
818 capt_rescmd_fifo_cnt ? sfifo_rescmd_depth :
-4-
==>
819 (sfifo_gencmd_pop || sfifo_rescmd_pop) ? (cmd_fifo_cnt_q-1) :
-5-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
- |
- |
Covered |
T5,T9,T7 |
| 0 |
0 |
0 |
1 |
- |
Covered |
T5,T9,T7 |
| 0 |
0 |
0 |
0 |
1 |
Covered |
T5,T9,T7 |
| 0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
829 assign cmd_hdr_busy_d =
830 capt_gencmd_fifo_cnt || capt_rescmd_fifo_cnt ? 1'b1 :
-1-
==>
831 cs_hw_cmd_handshake ? 1'b0 : cmd_hdr_busy_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T5,T9,T7 |
| 0 |
1 |
Covered |
T3,T22,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
910 assign csrng_fips_d =
911 !edn_enable_fo[CsrngFipsEn] ? 1'b0 :
-1-
==>
912 (packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
927 assign cs_rdata_capt_d = cs_rdata_capt_vld ? packer_cs_rdata[63:0] : cs_rdata_capt_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
929 assign cs_rdata_capt_vld_d =
930 !edn_enable_fo[CsrngDataVld] ? 1'b0 :
-1-
==>
931 cs_rdata_capt_vld ? 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
967 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
-1-
==>
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
967 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
-1-
==>
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T23,T9 |
| 0 |
0 |
Covered |
T1,T2,T3 |
967 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
-1-
==>
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T39,T17,T45 |
| 0 |
0 |
Covered |
T1,T2,T3 |
967 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
-1-
==>
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T39,T7,T49 |
| 0 |
0 |
Covered |
T1,T2,T3 |
967 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
-1-
==>
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T30,T40,T51 |
| 0 |
0 |
Covered |
T1,T2,T3 |
967 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
-1-
==>
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T22,T40,T54 |
| 0 |
0 |
Covered |
T1,T2,T3 |
967 assign edn_fips_d[i] = packer_ep_clr[i] ? 1'b0 :
-1-
==>
968 (packer_ep_push[i] && packer_ep_wready[i]) ? csrng_fips_q :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T39,T10,T40 |
| 0 |
0 |
Covered |
T1,T2,T3 |
223 if (!rst_ni) begin
-1-
224 cs_cmd_req_q <= '0;
==>
225 cs_cmd_req_vld_q <= '0;
226 cs_cmd_req_out_q <= '0;
227 cs_cmd_req_vld_out_q <= '0;
228 cs_cmd_req_vld_hold_q <= '0;
229 cmd_fifo_cnt_q <= '0;
230 csrng_fips_q <= '0;
231 edn_fips_q <= '0;
232 cs_rdata_capt_q <= '0;
233 cs_rdata_capt_vld_q <= '0;
234 cmd_rdy_q <= '0;
235 csrng_cmd_sts_q <= csrng_pkg::CMD_STS_SUCCESS;
236 csrng_sw_cmd_ack_q <= '0;
237 csrng_hw_cmd_sts_q <= csrng_pkg::CMD_STS_SUCCESS;
238 boot_mode_q <= '0;
239 auto_mode_q <= '0;
240 cmd_type_q <= {1'b0, csrng_pkg::INV};
241 cmd_reg_rdy_q <= '0;
242 cmd_hdr_busy_q <= 1'b0;
243 end else begin
244 cs_cmd_req_q <= cs_cmd_req_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
edn_core
Assertion Details
CsErrAcceptNoEntropy_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
35715 |
0 |
0 |
| T6 |
23340 |
0 |
0 |
0 |
| T9 |
2556 |
0 |
0 |
0 |
| T10 |
0 |
198 |
0 |
0 |
| T23 |
2164 |
136 |
0 |
0 |
| T24 |
879 |
0 |
0 |
0 |
| T25 |
1927 |
0 |
0 |
0 |
| T26 |
1926 |
0 |
0 |
0 |
| T28 |
0 |
218 |
0 |
0 |
| T30 |
991 |
0 |
0 |
0 |
| T39 |
3478 |
0 |
0 |
0 |
| T44 |
0 |
148 |
0 |
0 |
| T56 |
0 |
175 |
0 |
0 |
| T57 |
9324 |
0 |
0 |
0 |
| T62 |
849 |
0 |
0 |
0 |
| T71 |
0 |
136 |
0 |
0 |
| T88 |
0 |
185 |
0 |
0 |
| T114 |
0 |
193 |
0 |
0 |
| T115 |
0 |
227 |
0 |
0 |
| T116 |
0 |
217 |
0 |
0 |
CsErrIssueNoCommands_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11370796 |
35715 |
0 |
0 |
| T6 |
23340 |
0 |
0 |
0 |
| T9 |
2556 |
0 |
0 |
0 |
| T10 |
0 |
198 |
0 |
0 |
| T23 |
2164 |
136 |
0 |
0 |
| T24 |
879 |
0 |
0 |
0 |
| T25 |
1927 |
0 |
0 |
0 |
| T26 |
1926 |
0 |
0 |
0 |
| T28 |
0 |
218 |
0 |
0 |
| T30 |
991 |
0 |
0 |
0 |
| T39 |
3478 |
0 |
0 |
0 |
| T44 |
0 |
148 |
0 |
0 |
| T56 |
0 |
175 |
0 |
0 |
| T57 |
9324 |
0 |
0 |
0 |
| T62 |
849 |
0 |
0 |
0 |
| T71 |
0 |
136 |
0 |
0 |
| T88 |
0 |
185 |
0 |
0 |
| T114 |
0 |
193 |
0 |
0 |
| T115 |
0 |
227 |
0 |
0 |
| T116 |
0 |
217 |
0 |
0 |